DS26521 datasheet(21/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

21 of 258

NAME

TYPE

FUNCTION

RECEIVE FRAMER

RSER

Received Serial Data.

Received NRZ serial data. Updated on rising edges of

RCLK when the receive-side elastic store is disabled. Updated on the rising edges

of RSYSCLK when the receive-side elastic store is enabled. When IBO mode is

used, the RSER data is synchronous to to RSYSCLK. This is described in Section

8.8.2.

RCLK

Receive Clock.

A 1.544MHz (T1) or 2.048MHz (E1) clock that is used to clock

data through the receive-side framer. This clock is recovered from the signal at

RTIP and RRING. RSER data is output on the rising edge of RCLK. RCLK is used

to output RSER when the elastic store is not enabled or IBO is not used. When the

elastic store is enabled or IBO is used, the RSER is clocked by RSYSCLK.

RSYSCLK

Receive System Clock.

1.544MHz, 2.048MHz, 4.096MHz, 8.192MHz, or

16.384MHz receive backplane clock. Only used when the receive-side elastic store

function is enabled. Should be tied low in applications that do not use the receive-

side elastic store. Multiple of 2.048MHz is expected when the IBO mode is used.

RSYNC

I/O

Receive Synchronization.

If the receive-side elastic store is enabled, then this

signal is used to input a frame or multiframe boundary pulse. If set to output frame

boundaries, then RSYNC can be programmed to output double-wide pulses on

signaling frames in T1 mode. In E1 mode, RSYNC out can be used to indicate

CAS and CRC-4 multiframe. The DS26521 can accept H.100-compatible

synchronization signal. The default direction of this pin at power-up is input, as

determined by the RSIO control bit in the RIOCR.2 register.

RMSYNC/

RFSYNC

Receive Multiframe/Frame Synchronization.

A dual function pin to indicate

frame or multiframe synchronization. RFSYNC is an extracted 8kHz pulse, one

RCLK wide that identifies frame boundaries. RMSYNC is an extracted pulse, one

RCLK wide (elastic store disabled) or one RSYSCLK wide (elastic store enabled),

that identifies multiframe boundaries. When the receive elastic store is enabled,

the RMSYNC signal indicates the multiframe sync on the system (backplane) side

of the elastic store. In E1 mode, this pin can indicate either the CRC-4 or CAS

multiframe as determined by the RSMS2 control bit in the Receive I/O

Configuration register (RIOCR.1).

RSIG

Receive Signaling.

Outputs signaling bits in a PCM format. Updated on rising

edges of RCLK when the receive-side elastic store is disabled. Updated on the

rising edges of RSYSCLK when the receive-side elastic store is enabled.

AL/

RSIGF/

FLOS

Analog Loss/Receive-Signaling Freeze/Framer LOS.

Analog LOS reflects the

LOS (loss of signal) detected by the LIU front-end and framer LOS is LOS

detection by the corresponding framer; the same pins can reflect receive-signaling

freeze indications. This selection can be made by settings in the Global

Transceiver Clock Control register (GTCCR ).

If framer LOS is selected, this pin can be programmed to toggle high when the

framer detects an LOS condition, or when the signaling data is frozen via either

automatic or manual intervention. The indication is used to alert downstream

equipment of the condition.

RLF/

LTC

Receive Loss of Frame/Loss of Transmit Clock.

This pin can be programmed to

either toggle high when the synchronizer is searching for the frame and multiframe,

or to toggle high if the TCLK pin has not been toggled for approximately three clock

periods.

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