DS26521 datasheet(49/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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8.9.5.2 Receive Bit-Oriented Code (BOC) Controller

The DS26521 framer contains a BOC generator on the transmit side and a BOC detector on the receive side. The

BOC function is available only in T1, ESF mode in the data link bits. Table 8-14 shows the registers related to the

receive BOC operation.

Table 8-14. Registers Related to T1 Receive BOC

FRAMER

ADDRESSES

FUNCTION

Receive BOC Control Register

(T1RBOCC)

015h

Controls the receive BOC function.

Receive BOC Register (T1RBOC)

063h

Receive bit-oriented message.

Receive Latched Status Register 7(RLS7)

096h

Indicates changes to the receive bit-oriented

messages.

Receive Interrupt Mask Register 7 (RIM7)

0A6h

Mask bits for RBOC for generation of

interrupts.

In ESF mode, the DS26521 continuously monitors the receive message bits for a valid BOC message. The BOC

detect (BD) status bit at RLS7.0 is set once a valid message has been detected for a time determined by the

receive BOC filter bits RBF0 and RBF1 in the T1RBOCC register. The 6-bit BOC message is available in the

T1RBOC register. Once the user has cleared the BD bit, it remains clear until a new BOC is detected (or the same

BOC is detected following a BOC clear event). The BOC clear (BC) bit at RLS7.1 is set when a valid BOC is no

longer being detected for a time determined by the receive BOC disintegration bits RBD0 and RBD1 in the

T1RBOCC register.

The BD and BC status bits can create a hardware interrupt on the

INTB signal as enabled by the associated

interrupt mask bits in the RIM7 register.

8.9.5.3 Legacy T1 Transmit FDL

It is recommended that the DS26521’s built-in BOC or HDLC controllers be used for most applications requiring

access to the FDL. Table 8-16 shows the registers related to control of the transmit FDL.

Table 8-15. Registers Related to T1 Transmit FDL

FRAMER

ADDRESSES

FUNCTION

Transmit FDL Register (T1TFDL)

162h

FDL code used to insert transmit FDL.

Transmit Control Register 2 (TCR2)

182h

Defines the source of the FDL.

Transmit Latched Status Register 2 (TLS2)

191h

Transmit FDL empty bit.

Transmit Interrupt Mask Register 2 (HDLC)

(TIM2)

1A1h

Mask bit for TFDL empty.

When enabled with TCR2.7, the transmit section shifts out into the T1 data stream either the FDL (in the ESF

framing mode) or the Fs bits (in the D4 framing mode) contained in the Transmit FDL register (T1TFDL). When a

new value is written to the T1TFDL, it is multiplexed serially (LSB first) into the proper position in the outgoing T1

data stream. After the full eight bits have been shifted out, the framer signals the host controller that the buffer is

empty and that more data is needed by setting the TLS2.4 bit to a 1. The

INTB bit also toggles low if enabled via

TIM2.4. The user has 2ms to update the T1TFDL with a new value. If the T1TFDL is not updated, the old value in

the T1TFDL is transmitted once again. Note that in this mode, no zero stuffing is applied to the FDL data. It is

strongly suggested that the HDLC controller be used for FDL messaging applications.

In the D4 framing mode, the framer uses the T1TFDL register to insert the Fs framing pattern. To accomplish this,

the T1TFDL register must be programmed to 1Ch and TCR2.7 should be set to 0 (source Fs data from the T1TFDL

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