DS26521 datasheet(47/258 Pages) MAXIM

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DS26521 Single T1/E1/J1 Transceiver

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8.9.4.3.6 Receive-Signaling Freeze

The signaling data in the four multiframe signaling buffers is frozen in a known good state upon either a loss of

synchronization (OOF event), carrier loss, or change of frame alignment. In T1 mode, this action meets the

requirements of BellCore TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RSFE

control bit (RSIGC.1) should be set high. The user can force a freeze by setting the RSFF control bit (RSIGC.2)

high. The RSIGF output pin provides a hardware indication that a freeze is in effect. The four multiframe buffer

provides a three multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER pin if receive-

signaling reinsertion is enabled). When freezing is enabled (RSFE = 1), the signaling data is held in the last known

good state until the corrupting error condition subsides. When the error condition subsides, the signaling data is

held in the old state for at least an additional 9ms (4.5ms in D4 framing mode, 6ms for E1 mode) before being

allowed to be updated with new signaling data.

The receive-signaling registers are frozen and not updated during a loss-of-sync condition. They will contain the

most recent signaling information before the LOF occurred.

8.9.4.4 Transmit SLC-96 Operation (T1 Mode Only)

In an SLC-96-based transmission scheme, the standard Fs-bit pattern is robbed to make room for a set of

message fields. The SLC-96 multiframe is made up of six D4 superframes, thus it is 72 frames long. In the 72-

frame SLC-96 multiframe, 36 of the framing bits are the normal Ft pattern and the other 36 bits are divided into

alarm, maintenance, spoiler, and concentrator bits, as well as 12 bits of the normal Fs pattern. Additional SLC-96

information can be found in BellCore document TR-TSY-000008. Registers related to the transmit FDL are shown

in Table 8-12.

Table 8-12. Registers Related to SLC-96

FRAMER

ADDRESSES

FUNCTION

Transmit FDL Register (T1TFDL)

162h

For sending messages in transmit SLC-96 Ft/Fs

bits.

Transmit SLC-96 Data Link Registers 1

to 3 (T1TSLC1:T1TSLC3)

164h, 165h, 166h

Registers that control the SLC-96 overhead

values.

Transmit Control Register 2 TCR2)

182h

Transmit control for data selection source for the

Ft/Fs bits.

Transmit Latched Status Register 1

(TLS1)

190h

Status bit for indicating transmission of data link

buffer.

Receive SLC-96 Data Link Registers 1

to 3 (T1RSLC1:T1RSLC3)

064h, 065h, 066h

—

Receive Latched Status Register 7

(RLS7)

096h

Receive SLC-96 alignment event.

The T1TFDL register is used to insert the SLC-96 message fields. To insert the SLC-96 message using the

T1TFDL register, the user should configure the DS26521 as shown:

•

TCR2.6 (TSLC96) = 1

Enable transmit SLC-96.

•

TCR2.7 (TFDLS) = 0

Source FS bits via TFDL or SLC-96 formatter.

•

TCR3.2 (TFM) = 1

D4 framing mode.

•

TCR1.6 (TFPT) = 0

Do not “pass through” TSER F-bits.

The DS26521 automatically inserts the 12-bit alignment pattern in the Fs bits for the SLC-96 data link frame. Data

from T1TSLC1:T1TSLC3 is inserted into the remaining Fs-bit locations of the SLC-96 multiframe. The status bit

TSLC96 located at TLS1.4 is set to indicate that the SLC-96 data link buffer has been transmitted and that the user

should write new message data into T1TSLC1:T1TSLC3. The host has 9ms after the assertion of TLS1.4 to write

the registers T1TSLC1:T1TSLC3. If no new data is provided in these registers, the previous values are

retransmitted.

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