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PIC24F04KA201 датащи(PDF) 12 Page - Microchip Technology |
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PIC24F04KA201 датащи(HTML) 12 Page - Microchip Technology |
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12 / 224 page ![]() PIC24F04KA201 FAMILY DS39937B-page 10 Preliminary © 2009 Microchip Technology Inc. FIGURE 1-1: PIC24F04KA201 FAMILY GENERAL BLOCK DIAGRAM Instruction Decode and Control 16 PCH PCL 16 Program Counter 16-Bit ALU 23 24 Data Bus Inst Register 16 Divide Support Inst Latch 16 EA MUX Read AGU Write AGU 16 16 8 Interrupt Controller PSV and Table Data Access Control Block Stack Control Logic Repeat Control Logic Data Latch Data RAM Address Latch Address Latch Program Memory Data Latch 16 Address Bus 23 Control Signals 16 16 16 x 16 W Reg Array Multiplier 17x17 PORTA(1) RA<6:0> PORTB(1) RB<15:12, 9:7> Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. Comparators Timer2/3 Timer1 CTMU IC1 ADC 10-Bit OC1/PWM SPI1 I2C1 CN1-17(1) UART1 OSCI/CLKI OSCO/CLKO VDD, Timing Generation VSS MCLR Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR Precision Reference Band Gap FRC/LPRC Oscillators DSWDT HLVD REFO RB<4, 2:0> |
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