PIC24F04KA201 datasheet(59/224 Pages) MICROCHIP

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Preliminary

DS39937B-page 57

PIC24F04KA201 FAMILY

7.0

INTERRUPT CONTROLLER

The PIC24F interrupt controller reduces the numerous

peripheral interrupt request signals to a single interrupt

request signal to the CPU. It has the following features:

• Up to eight processor exceptions and

software traps

• Seven user-selectable priority levels

• Interrupt Vector Table (IVT) with up to 118 vectors

• Unique vector for each interrupt or exception

source

• Fixed priority within a specified user priority level

• Fixed interrupt entry and return latencies

7.1

Interrupt Vector (IVT) Table

The IVT is displayed in Figure 7-1. The IVT resides in

the program memory, starting at location 000004h. The

IVT contains 126 vectors, consisting of eight

non-maskable trap vectors, plus, up to 118 sources of

interrupt. In general, each interrupt source has its own

vector. Each interrupt vector contains a 24-bit wide

address. The value programmed into each interrupt

vector location is the starting address of the associated

Interrupt Service Routine (ISR).

Interrupt vectors are prioritized in terms of their natural

priority; this is linked to their position in the vector table.

All other things being equal, lower addresses have a

higher natural priority. For example, the interrupt

associated with vector 0 will take priority over interrupts

at any other vector address.

PIC24F04KA201

family

devices

implement

non-maskable traps and unique interrupts; these are

summarized in Table 7-1 and Table 7-2.

7.2

Reset Sequence

A device Reset is not a true exception because the

interrupt controller is not involved in the Reset process.

The PIC24F devices clear their registers in response to

a Reset, which forces the Program Counter (PC) to

zero. The microcontroller then begins program execu-

tion at location 000000h. The user programs a GOTO

instruction at the Reset address, which redirects the

program execution to the appropriate start-up routine.

FIGURE 7-1:

PIC24F INTERRUPT VECTOR TABLE

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended to be a comprehensive reference

source. For more information on the

Interrupt Controller, refer to the “PIC24F

Family Reference Manual”

, Section 8.

“Interrupts”

(DS39707).

Note:

Any unimplemented or unused vector

locations

the

IVT

should

programmed with the address of a default

interrupt handler routine that contains a

RESET

instruction.

Reset – GOTO Instruction

000000h

Reset – GOTO Address

000002h

Reserved

000004h

Oscillator Fail Trap Vector

Address Error Trap Vector

Stack Error Trap Vector

Math Error Trap Vector

Reserved

Interrupt Vector 0

000014h

Interrupt Vector 1

—

Interrupt Vector 52

00007Ch

Interrupt Vector 53

00007Eh

Interrupt Vector 54

000080h

—

Interrupt Vector 116

0000FCh

Interrupt Vector 117

0000FEh

Interrupt Vector Table (IVT)(1)

Note 1:

See Table 7-2 for the interrupt vector list.

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