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PIC24F04KA201 датащи(PDF) 29 Page - Microchip Technology |
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PIC24F04KA201 датащи(HTML) 29 Page - Microchip Technology |
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29 / 224 page ![]() © 2009 Microchip Technology Inc. Preliminary DS39937B-page 27 PIC24F04KA201 FAMILY 4.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is displayed in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the Program Space Visibility (PSV) area (see Section 4.3.3 “Reading Data From Program Memory Using Program Space Visibility” ). PIC24F04KA201 family devices implement a total of 768 words of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all the data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. FIGURE 4-3: DATA SPACE MEMORY MAP FOR PIC24F04KA201 FAMILY DEVICES 0000h 07FEh FFFEh LSB Address LSB MSB MSB Address 0001h 07FFh 0DFFh FFFFh 8001h 8000h 7FFFh 0801h 0800h Near 09FEh SFR SFR Space Data RAM 7FFFh Program Space Visibility Area Note: Data memory areas are not shown to scale. 1FFEh 1FFF Space Data Space Implemented Data RAM Unimplemented Read as ‘0’ |
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