PIC24F04KA201 datasheet(96/224 Pages) MICROCHIP

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PIC24F04KA201 FAMILY

DS39937B-page 94

Preliminary

9.2.4.5

Deep Sleep WDT

To enable the DSWDT in Deep Sleep mode, program

the Configuration bit, DSWDTEN (FDS<7>). The

device Watchdog Timer (WDT) need not be enabled for

the DSWDT to function. Entry into Deep Sleep mode

automatically resets the DSWDT.

The DSWDT clock source is selected by the

DSWDTOSC

Configuration

bit

(FDS<4>).

The

postscaler

options

are

programmed

the

DSWDTPS<3:0> Configuration bits (FDS<3:0>). The

minimum time-out period that can be achieved is

2.1 ms and the maximum is 25.7 days. For more

details on the FDS Configuration register and DSWDT

configuration options, refer to Section 23.0 “Special

Features”

9.2.4.6

Switching Clocks in Deep Sleep Mode

The DSWDT may run from either SOSC or the LPRC

clock source. This allows the DSWDT to run without

requiring both the LPRC and SOSC to be enabled

together, reducing power consumption.

Under certain circumstances, it is possible for the

DSWDT clock source to be off when entering Deep

Sleep mode. In this case, the clock source is turned on

automatically (if DSWDT is enabled), without the need

for software intervention. However, this can cause a

delay in the start of the DSWDT counters. In order to

avoid this delay when using SOSC as a clock source,

the application can activate SOSC prior to entering

Deep Sleep mode.

9.2.4.7

Checking and Clearing the Status of

Deep Sleep

Upon entry into Deep Sleep mode, the status bit,

DPSLP (RCON<10>), becomes set and must be

cleared by the software.

On power-up, the software should read this status bit to

determine if the Reset was due to an exit from Deep

Sleep mode and clear the bit if it is set. Of the four

possible combinations of DPSLP and POR bit states,

three cases can be considered:

• Both the DPSLP and POR bits are cleared. In this

case, the Reset was due to some event other

than a Deep Sleep mode exit.

• The DPSLP bit is clear, but the POR bit is set.

This is a normal POR.

• Both the DPSLP and POR bits are set. This

means that Deep Sleep mode was entered, the

device was powered down and Deep Sleep mode

was exited.

9.2.4.8

Power-on Resets (PORs)

VDD voltage is monitored to produce PORs. Since exit-

ing from Deep Sleep functionally looks like a POR, the

technique described in Section 9.2.4.7 “Checking

and Clearing the Status of Deep Sleep”

should be

used to distinguish between Deep Sleep and a true

POR event.

When a true POR occurs, the entire device including

all Deep Sleep logic, (Deep Sleep registers, DSWDT,

etc.) is reset.

9.2.4.9

Summary of Deep Sleep Sequence

To review, these are the necessary steps involved in

invoking and exiting Deep Sleep mode:

Device exits Reset and begins to execute its

application code.

If DSWDT functionality is required, program the

appropriate Configuration bit.

Select the appropriate clock(s) for the DSWDT

(optional).

Enable and configure the DSWDT (optional).

Write context data to the DSGPRx registers

(optional).

Enable the INT0 interrupt (optional).

Set the DSEN bit in the DSCON register.

Enter Deep Sleep by issuing a PWRSV

#SLEEP_MODE

command.

Device exits Deep Sleep when a wake-up event

occurs.

10. The DSEN bit is automatically cleared.

11. Read and clear the DPSLP status bit in RCON,

and the DSWAKE status bits.

12. Read the DSGPRx registers (optional).

13. Once all state related configurations are

complete, clear the RELEASE bit.

14. Application resumes normal operation.

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