PIC24F04KA201 datasheet(98/224 Pages) MICROCHIP

98 / 224 page

PIC24F04KA201 FAMILY

DS39937B-page 96

Preliminary

DSWSRC: DEEP SLEEP WAKE-UP SOURCE REGISTER(1)

U-0

R/W-0, HS

—

—DSINT0

bit 15

bit 8

R/W-0, HS

U-0

R/W-0, HS

U-0

R/W-0, HS

U-0

R/W-0, HS

DSFLT

—

—DSWDT

—DSMCLR

—

DSPOR(2,3)

bit 7

bit 0

Legend:

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-9

Unimplemented:

Read as ‘0’

bit 8

DSINT0:

Interrupt-on-Change bit

= Interrupt-on-change was asserted during Deep Sleep

= Interrupt-on-change was not asserted during Deep Sleep

bit 7

DSFLT:

Deep Sleep Fault Detected bit

= A Fault occurred during Deep Sleep, and some Deep Sleep configuration settings may have been

corrupted

= No Fault was detected during Deep Sleep

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

DSWDT:

Deep Sleep Watchdog Timer Time-out bit

= The Deep Sleep Watchdog Timer timed out during Deep Sleep

= The Deep Sleep Watchdog Timer did not time out during Deep Sleep

bit 3

Unimplemented:

Read as ‘0’

bit 2

DSMCLR:

MCLR Event bit

= The MCLR pin was active and was asserted during Deep Sleep

= The MCLR pin was not active, or was active, but not asserted during Deep Sleep

bit 1

Unimplemented:

Read as ‘0’

bit 0

DSPOR:

Power-on Reset Event bit(2,3)

= The VDD supply POR circuit was active and a POR event was detected

= The VDD supply POR circuit was not active, or was active but did not detect a POR event

Note 1:

All register bits are cleared when the DSCON<DSEN> bit is set.

All register bits are reset only in the case of a POR event outside Deep Sleep mode, except the DSPOR

bit, which does not reset on a POR event that is caused due to a Deep Sleep exit.

Unlike the other bits in this register, this bit can be set outside of Deep Sleep.

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