PIC24F04KA201 datasheet(95/224 Pages) MICROCHIP

95 / 224 page

Preliminary

DS39937B-page 93

PIC24F04KA201 FAMILY

Exiting Deep Sleep mode generally does not retain the

state of the device and is equivalent to a Power-on

Reset (POR) of the device. Exceptions to this include

the DSGPRx registers and DSWSRC.

Wake-up events that occur from the time Deep Sleep

exits until the time the POR sequence completes are

ignored, and are not be captured in the DSWAKE

The sequence for exiting Deep Sleep mode is:

After a wake-up event, the device exits Deep

Sleep and performs a POR. The DSEN bit is

cleared automatically. Code execution resumes

at the Reset vector.

To determine if the device exited Deep Sleep,

read the Deep Sleep bit, DPSLP (RCON<10>).

This bit will be set if there was an exit from Deep

Sleep mode. If the bit is set, clear it.

Determine the wake-up source by reading the

DSWAKE register.

Determine if a DSBOR event occurred during

Deep Sleep mode by reading the DSBOR bit

(DSCON<1>).

If application context data has been saved, read

it back from the DSGPR0 and DSGPR1

registers.

Clear the RELEASE bit (DSCON<0>).

9.2.4.3

Saving Context Data with the

DSGPR0/DSGPR1 Registers

As exiting Deep Sleep mode causes a POR, most

Special Function Registers reset to their default POR

values. In addition, because VDDCORE power is not

supplied in Deep Sleep mode, information in data RAM

may be lost when exiting this mode.

Applications which require critical data to be saved

prior to Deep Sleep may use the Deep Sleep General

Purpose registers, DSGPR0 and DSGPR1, or data

EEPROM (if available). Unlike other SFRs, the con-

tents of these registers are preserved while the device

is in Deep Sleep mode. After exiting Deep Sleep,

software can restore the data by reading the registers

and clearing the RELEASE bit (DSCON<0>).

9.2.4.4

I/O Pins During Deep Sleep

During Deep Sleep, the general purpose I/O pins retain

their previous states and the Secondary Oscillator

(SOSC) will remain running, if enabled. Pins that are

configured as inputs (TRIS bit set) prior to entry into

Deep Sleep remain high-impedance during Deep

Sleep. Pins that are configured as outputs (TRIS bit

clear) prior to entry into Deep Sleep remain as output

pins during Deep Sleep. While in this mode, they con-

tinue to drive the output level determined by their

corresponding LAT bit at the time of entry into Deep

Sleep.

Once the device wakes back up, all I/O pins continue to

maintain their previous states, even after the device

has finished the POR sequence and is executing appli-

cation code again. Pins configured as inputs during

Deep Sleep remain high-impedance and pins config-

ured as outputs continue to drive their previous value.

After waking up, the TRIS and LAT registers, and the

SOSCEN bit (OSCCON<1>) are reset. If firmware

modifies any of these bits or registers, the I/O will not

immediately go to the newly configured states. Once

the firmware clears the RELEASE bit (DSCON<0>) the

I/O pins are “released”. This causes the I/O pins to take

the states configured by their respective TRIS and LAT

bit values.

This means that keeping the SOSC running after

waking up requires the SOSCEN bit to be set before

clearing RELEASE.

If the Deep Sleep BOR (DSBOR) is enabled, and a

DSBOR or a true POR event occurs during Deep

Sleep, the I/O pins will be immediately released similar

to clearing the RELEASE bit. All previous state infor-

mation will be lost, including the general purpose

DSGPR0 and DSGPR1 contents.

If a MCLR Reset event occurs during Deep Sleep, the

DSGPRx, DSCON and DSWAKE registers will remain

valid and the RELEASE bit will remain set. The state of

the SOSC also will be retained. The I/O pins, however,

will be reset to their MCLR Reset state. Since

RELEASE is still set, changes to the SOSCEN bit

(OSCCON<1>) cannot take effect until the RELEASE

bit is cleared.

In all other Deep Sleep wake-up cases, application

firmware must clear the RELEASE bit in order to

reconfigure the I/O pins.

Note:

Any interrupt pending when entering Deep

Sleep mode is cleared,

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