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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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PIC24F04KA201 датащи(PDF) 86 Page - Microchip Technology |
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PIC24F04KA201 датащи(HTML) 86 Page - Microchip Technology |
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86 / 224 page  PIC24F04KA201 FAMILY DS39937B-page 84 Preliminary © 2009 Microchip Technology Inc. bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 Unimplemented: Read as ‘0’ bit 5 LOCK: PLL Lock Status bit(2) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 Unimplemented: Read as ‘0’ bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC<2:0> bits 0 = Oscillator switch is complete REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) Note 1: Reset values for these bits are determined by the FNOSC Configuration bits. 2: Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. |
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