PIC24F04KA201 datasheet(47/224 Pages) MICROCHIP

47 / 224 page

Preliminary

DS39937B-page 45

PIC24F04KA201 FAMILY

NVMCON: FLASH MEMORY CONTROL REGISTER

R/SO-0, HC

R/W-0

U-0

WREN

WRERR

PGMONLY

—

bit 15

bit 8

U-0

R/W-0

—

ERASE

NVMOP5(1)

NVMOP4(1)

NVMOP3(1)

NVMOP2(1)

NVMOP1(1)

NVMOP0(1)

bit 7

bit 0

Legend:

SO = Settable Only bit

HC = Hardware Clearable bit

-n = Value at POR

‘1’ = Bit is set

R = Readable bit

W = Writable bit

‘0’ = Bit is cleared

x = Bit is unknown

U = Unimplemented bit, read as ‘0’

bit 15

WR:

Write Control bit

= Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is

cleared by hardware once the operation is complete

= Program or erase operation is complete and inactive

bit 14

WREN:

Write Enable bit

= Enable Flash program/erase operations

= Inhibit Flash program/erase operations

bit 13

WRERR:

Write Sequence Error Flag bit

= An improper program or erase sequence attempt or termination has occurred (bit is set automatically

on any set attempt of the WR bit)

= The program or erase operation completed normally

bit 12

PGMONLY:

Program Only Enable bit

bit 11-7

Unimplemented:

Read as ‘0’

bit 6

ERASE:

Erase/Program Enable bit

= Perform the erase operation specified by NVMOP<5:0> on the next WR command

= Perform the program operation specified by NVMOP<5:0> on the next WR command

bit 5-0

NVMOP<5:0>:

Programming Operation Command Byte bits(1)

Erase Operations (when ERASE bit is ‘1’):

1010xx

= Erase entire boot block (including code-protected boot block)(2)

1001xx

= Erase entire memory (including boot block, configuration block, general block)(2)

011010

= Program/erase 4 rows of Flash memory(3)

011001

= Program/erase 2 rows of Flash memory(3)

011000

= Program/erase 1 row of Flash memory(3)

0101xx

= Erase entire configuration block (except code protection bits)

0011xx

= Erase entire general memory block programming operations

Note 1:

All other combinations of NVMOP<5:0> are no operation.

Available in ICSP™ mode only. Refer to device programming specification.

The address in the Table Pointer decides which rows will be erased.

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