PIC24F04KA201 datasheet(113/224 Pages) MICROCHIP

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Preliminary

DS39937B-page 111

PIC24F04KA201 FAMILY

14.0

OUTPUT COMPARE

14.1

Setup for Single Output Pulse

Generation

When the OCM control bits (OC1CON<2:0>) are set to

‘100’, the selected output compare channel initializes

the OC1 pin to the low state and generates a single

output pulse.

To generate a single output pulse, the following steps

are required (these steps assume the timer source is

initially turned off, but this is not a requirement for the

module operation):

Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

Write the values computed in steps 2 and 3

above into the Output Compare 1 register,

OC1R, and the Output Compare 1 Secondary

Set Timer Period register, PRy, to value equal to

or greater than the value in OC1RS, the Output

Compare 1 Secondary register.

Set the OCM bits to ‘100’ and the OCTSEL

(OC1CON<3>) bit to the desired timer source.

The OC1 pin state will now be driven low.

Set the TON (TyCON<15>) bit to ‘1’, which

enables the compare time base to count.

Upon the first match between TMRy and OC1R,

the OC1 pin will be driven high.

When the incrementing timer, TMRy, matches

the Output Compare 1 Secondary register,

OC1RS,

the

second

and

trailing

edge

(high-to-low) of the pulse is driven onto the OC1

pin. No additional pulses are driven onto the

OC1 pin and it remains low. As a result of the

second compare match event, the OC1IF inter-

rupt flag bit is set, which will result in an interrupt

if it is enabled, by setting the OC1IE bit. For

further information on peripheral interrupts, refer

to Section 7.0 “Interrupt Controller”.

10. To initiate another single pulse output, change

the Timer and Compare register settings, if

needed, and then issue a write to set the OCM

bits to ‘100’. Disabling and re-enabling of the

timer and clearing the TMRy register are not

required, but may be advantageous for defining

a pulse from a known event time boundary.

The output compare module does not have to be

disabled after the falling edge of the output pulse.

Another pulse can be initiated by rewriting the value of

the OC1CON register.

14.2

Setup for Continuous Output

Pulse Generation

When the OCM control bits (OC1CON<2:0>) are set to

‘101’, the selected output compare channel initializes

the OC1 pin to the low state and generates output

pulses on each and every compare match event.

For the user to configure the module for the generation

of a continuous stream of output pulses, the following

steps are required (these steps assume the timer

source is initially turned off, but this is not a requirement

for the module operation):

Determine the instruction clock cycle time. Take

into account the frequency of the external clock

to the timer source (if one is used) and the timer

prescaler settings.

Calculate time to the rising edge of the output

pulse relative to the TMRy start value (0000h).

Calculate the time to the falling edge of the pulse

based on the desired pulse width and the time to

the rising edge of the pulse.

Write the values computed in step 2 and 3 above

into the Output Compare 1 register, OC1R, and the

Output Compare 1 Secondary register, OC1RS,

respectively.

Set the Timer Period register, PRy, to a value

equal to or greater than the value in OC1RS.

Set the OCM bits to ‘101’ and the OCTSEL bit to

the desired timer source. The OC1 pin state will

now be driven low.

Enable the compare time base by setting the

TON (TyCON<15>) bit to ‘1’.

Upon the first match between TMRy and OC1R,

the OC1 pin will be driven high.

When the compare time base, TMRy, matches the

OC1RS, the second and trailing edge (high-to-low)

of the pulse is driven onto the OC1 pin.

10. As a result of the second compare match event,

the OC1IF interrupt flag bit is set.

11. When the compare time base and the value in its

respective Timer Period register match, the TMRy

12. Steps 8 through 11 are repeated and a con-

tinuous

stream

pulses

generated

indefinitely. The OC1IF flag is set on each

OC1RS/TMRy compare match event.

Note:

This data sheet summarizes the features

of this group of PIC24F devices. It is not

intended

comprehensive

reference source. For more information

on Output Compare, refer to the “PIC24F

Family Reference Manual”

, Section 16.

“Output Compare”

(DS39706).

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