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P89LPC915FDH датащи(PDF) 74 Page - NXP Semiconductors

номер детали P89LPC915FDH
подробное описание детали  8-bit microcontrollers with accelerated two-clock 80C51 core 2 kB 3 V flash with 8-bit A/D converter
PDF  75 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
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P89LPC915FDH датащи(HTML) 74 Page - NXP Semiconductors

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P89LPC915_916_917_5
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 05 — 15 December 2009
74 of 75
continued >>
NXP Semiconductors
P89LPC915/916/917
8-bit microcontrollers with accelerated two-clock 80C51 core
19. Contents
1
General description . . . . . . . . . . . . . . . . . . . . . . 1
2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2.1
Principal features . . . . . . . . . . . . . . . . . . . . . . . 1
2.2
Additional features . . . . . . . . . . . . . . . . . . . . . . 1
3
Product comparison overview . . . . . . . . . . . . . 2
4
Ordering information . . . . . . . . . . . . . . . . . . . . . 3
4.1
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3
5
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 7
7
Pinning information . . . . . . . . . . . . . . . . . . . . . . 9
7.1
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7.2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . 11
8
Functional description . . . . . . . . . . . . . . . . . . 18
8.1
Special function registers . . . . . . . . . . . . . . . . 18
8.2
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8.3.1
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . 31
8.3.2
CPU clock (OSCCLK). . . . . . . . . . . . . . . . . . . 31
8.3.3
Clock output (P89LPC917) . . . . . . . . . . . . . . . 31
8.4
On-chip RC oscillator option . . . . . . . . . . . . . . 31
8.5
Watchdog oscillator option . . . . . . . . . . . . . . . 31
8.6
External clock input option . . . . . . . . . . . . . . . 32
8.7
CCLK wake-up delay . . . . . . . . . . . . . . . . . . . 32
8.8
CCLK modification: DIVM register . . . . . . . . . 32
8.9
Low power select . . . . . . . . . . . . . . . . . . . . . . 33
8.10
Memory organization . . . . . . . . . . . . . . . . . . . 33
8.11
Data RAM arrangement . . . . . . . . . . . . . . . . . 33
8.12
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.12.1
External interrupt inputs . . . . . . . . . . . . . . . . . 34
8.13
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8.13.1
Port configurations . . . . . . . . . . . . . . . . . . . . . 36
8.13.1.1
Quasi-bidirectional output configuration . . . . . 36
8.13.1.2
Open-drain output configuration . . . . . . . . . . . 37
8.13.1.3
Input-only configuration . . . . . . . . . . . . . . . . . 37
8.13.1.4
Push-pull output configuration . . . . . . . . . . . . 37
8.13.2
Port 0 analog functions . . . . . . . . . . . . . . . . . . 37
8.13.3
Additional port features. . . . . . . . . . . . . . . . . . 37
8.14
Power monitoring functions. . . . . . . . . . . . . . . 38
8.14.1
Brownout detection . . . . . . . . . . . . . . . . . . . . . 38
8.14.2
Power-on detection . . . . . . . . . . . . . . . . . . . . . 38
8.15
Power reduction modes . . . . . . . . . . . . . . . . . 38
8.15.1
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
8.15.2
Power-down mode . . . . . . . . . . . . . . . . . . . . . 38
8.15.3
Total Power-down mode . . . . . . . . . . . . . . . . . 39
8.16
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
8.17
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . 39
8.17.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.17.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.17.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.17.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.17.5
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
8.17.6
Timer overflow toggle output . . . . . . . . . . . . . 40
8.18
RTC/system timer. . . . . . . . . . . . . . . . . . . . . . 40
8.19
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.19.1
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.19.2
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.19.3
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.19.4
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
8.19.5
Baud rate generator and selection . . . . . . . . . 42
8.19.6
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.19.7
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . 42
8.19.8
Double buffering . . . . . . . . . . . . . . . . . . . . . . . 42
8.19.9
Transmit interrupts with double buffering
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . 42
8.19.10
The 9th bit (bit 8) in double buffering
(Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . . . 43
8.20
I2C-bus serial interface . . . . . . . . . . . . . . . . . . 43
8.21
SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
8.21.1
Typical SPI configurations . . . . . . . . . . . . . . . 46
8.22
Analog comparators . . . . . . . . . . . . . . . . . . . . 48
8.22.1
Internal reference voltage. . . . . . . . . . . . . . . . 48
8.22.2
Comparator interrupt . . . . . . . . . . . . . . . . . . . 48
8.22.3
Comparators and power reduction modes . . . 48
8.23
KBI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
8.24
Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 50
8.25
Additional features . . . . . . . . . . . . . . . . . . . . . 50
8.25.1
Software reset . . . . . . . . . . . . . . . . . . . . . . . . 50
8.25.2
Dual data pointers . . . . . . . . . . . . . . . . . . . . . 50
8.26
Flash program memory . . . . . . . . . . . . . . . . . 51
8.26.1
General description . . . . . . . . . . . . . . . . . . . . 51
8.26.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
8.26.3
Flash organization . . . . . . . . . . . . . . . . . . . . . 51
8.26.4
Using flash as data storage . . . . . . . . . . . . . . 51
8.26.5
Flash programming and erasing. . . . . . . . . . . 51
8.26.6
ICP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.26.7
IAP-Lite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
8.26.8
Power-on reset code execution . . . . . . . . . . . 52
8.26.9
Hardware activation of the alternate code . . . 52
8.27
User configuration bytes. . . . . . . . . . . . . . . . . 52
8.28
User sector security bytes . . . . . . . . . . . . . . . 53
9
A/D converter . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.1
General description . . . . . . . . . . . . . . . . . . . . 53
9.2
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
9.3
Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . 54



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