P89LPC915FDH datasheet(52/75 Pages) NXP

52 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

52 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.26.6 ICP

ICP is performed without removing the microcontroller from the system. The ICP facility

consists of internal hardware resources to facilitate remote programming of the

P89LPC915/916/917 through a two-wire serial interface. The NXP ICP facility has made

in-circuit programming in an embedded application—using commercially available

programmers—possible with a minimum of additional expense in components and circuit

board area. The ICP function uses ﬁve pins. Only a small connector needs to be available

to interface your application to a commercial programmer in order to use this feature.

Additional details may be found in the P89LPC915/916/917

User’s Manual.

8.26.7 IAP-Lite

IAP-Lite is performed in the application under the control of the microcontroller’s ﬁrmware.

The IAP facility consists of internal hardware resources to facilitate programming and

erasing. The IAP-Lite operations are accomplished through the use of four SFRs

consisting of a control/status register, a data register, and two address registers.

Additional details may be found in the P89LPC915/916/917

User’s Manual.

8.26.8 Power-on reset code execution

The P89LPC915/916/917 contains two special ﬂash elements: the Boot Vector and the

Boot Status bit. Following reset, the P89LPC915/916/917 examines the contents of the

Boot Status bit. If the Boot Status bit is set to zero, power-up execution starts at location

0000H, which is the normal start address of the user’s application code. When the Boot

Status bit is set to a value other than zero, the contents of the Boot Vector are used as the

high byte of the execution address and the low byte is set to 00H.

Table 13 shows the factory default Boot Vector setting for this device. While these devices

do not contain a factory bootloader, the Boot Vector and Status bit do provide a

mechanism for an alternate code execution at reset.

8.26.9 Hardware activation of the alternate code

The alternate code execution address can be forced during a power-on sequence (see the

P89LPC915/916/917

User’s Manual for speciﬁc information). This has the same effect as

having a non-zero status byte. This allows an application to be built that will normally

execute user code starting at address 0000H but can be manually forced into executing

from an alternated address using the Boot Vector. After programming the ﬂash, the status

byte should be programmed to zero in order to allow execution of the user’s application

code beginning at address 0000H.

8.27 User conﬁguration bytes

Some user-conﬁgurable features of the P89LPC915/916/917 must be deﬁned at power-up

and therefore cannot be set by the program after start of execution. These features are

conﬁgured through the use of the ﬂash byte UCFG1. Please see the P89LPC915/916/917

User’s Manual for additional details.

Table 13.

Default boot vector and Status bit values

Device

Default boot vector

Default Status bit

P89LPC915

00H

P89LPC916

00H

P89LPC917

00H

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