P89LPC915FDH datasheet(37/75 Pages) NXP

37 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

37 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

The P89LPC915/916/917 is a 3 V device, but the pins are 5 V tolerant. In

quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current ﬂowing

from the pin to VDD, causing extra power consumption. Therefore, applying 5 V in

quasi-bidirectional mode is discouraged.

A quasi-bidirectional port pin has a Schmitt triggered input that also has a glitch

suppression circuit.

8.13.1.2

Open-drain output conﬁguration

The open-drain output conﬁguration turns off all pull-ups and only drives the pull-down

transistor of the port driver when the port latch contains a logic 0. To be used as a logic

output, a port conﬁgured in this manner must have an external pull-up, typically a resistor

tied to VDD.

An open-drain port pin has a Schmitt triggered input that also has a glitch suppression

circuit.

8.13.1.3

Input-only conﬁguration

The input-only port conﬁguration has no output drivers. It is a Schmitt triggered input that

also has a glitch suppression circuit.

8.13.1.4

Push-pull output conﬁguration

The push-pull output conﬁguration has the same pull-down structure as both the

open-drain and the quasi-bidirectional output modes, but provides a continuous strong

pull-up when the port latch contains a logic 1. The push-pull mode may be used when

more source current is needed from a port output. A push-pull port pin has a

Schmitt triggered input that also has a glitch suppression circuit.

8.13.2 Port 0 analog functions

The P89LPC915/916/917 incorporates two Analog Comparators. In order to give the best

analog function performance and to minimize power consumption, pins that are being

used for analog functions must have the digital outputs and digital inputs disabled.

Digital outputs are disabled by putting the port output into the Input-Only

(high-impedance) mode.

Digital inputs on Port 0 may be disabled through the use of the PT0AD register. On any

reset, PT0AD bits default to ‘0’s to enable digital functions.

8.13.3 Additional port features

After power-up, all pins are in Input-Only mode. After power-up, all I/O pins except P1.5,

may be conﬁgured by software.

• Pin P1.5 is input only.

• Pins P1.2 and P1.3 are conﬁgurable for either input-only or open-drain.

Every output on the P89LPC915/916/917 has been designed to sink typical LED drive

current. However, there is a maximum total output current for all ports which must not be

exceeded. Please refer to Table 15 “Static characteristics” for detailed speciﬁcations.

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