P89LPC915FDH datasheet(32/75 Pages) NXP

32 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

32 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.6 External clock input option

In this conﬁguration, the processor clock is derived from an external source driving the

CLKIN pin. The rate may be from 0 Hz up to 18 MHz.

When using an external clock input frequency above 12 MHz, the reset input

function of P1.5 must be enabled. An external circuit is required to hold the device

in reset at power-up until VDD has reached its speciﬁed level. When system power is

removed VDD will fall below the minimum speciﬁed operating voltage. When using

an external clock input frequency above 12 MHz, in some applications, an external

brownout detect circuit may be required to hold the device in reset when VDD falls

below the minimum speciﬁed operating voltage.

8.7 CCLK wake-up delay

The P89LPC915/916/917 has an internal wake-up timer that delays the clock until it

stabilizes. The delay is 224 OSCCLK cycles plus 60

µsto100 µs.

8.8 CCLK modiﬁcation: DIVM register

The OSCCLK frequency can be divided down up to 510 times by conﬁguring a dividing

CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can

retain the ability to respond to events that would not exit Idle mode by executing its normal

program at a lower rate. This can also allow bypassing the oscillator start-up time in cases

where Power-down mode would otherwise be used. The value of DIVM may be changed

by the program at any time without interrupting code execution.

Fig 11. Block diagram of oscillator control

÷2

002aaa831

RTC

CPU

WDT

DIVM

CCLK

OSCCLK

XCLK

RCCLK

I2C

peripheral clock

TIMERS 1 AND 0

CLKIN

OSCILLATOR

WATCHDOG

OSCILLATOR

(7.3728 MHz)

(400 kHz)

PCLK

RCCLK

SPI

(P89LPC916)

RTCS1:0

ADC1/DAC1

UART

BAUD RATE

GENERATOR

CLKOUT

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