P89LPC915FDH datasheet(31/75 Pages) NXP

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P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

31 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.2 Enhanced CPU

The P89LPC915/916/917 uses an enhanced 80C51 CPU which runs at six times the

speed of standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and

most instructions execute in one or two machine cycles.

8.3 Clocks

8.3.1 Clock deﬁnitions

The P89LPC915/916/917 device has several internal clocks as deﬁned below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock

sources (see Figure 11) and can also be optionally divided to a slower frequency (see

Section 8.8 “CCLK modiﬁcation: DIVM register”).

Note: fosc is deﬁned as the OSCCLK frequency.

CCLK — CPU clock; output of the clock divider. There are two CCLK cycles per machine

cycle, and most instructions are executed in one to two machine cycles (two or four CCLK

cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.

PCLK — Clock for the various peripheral devices and is CCLK

⁄

8.3.2 CPU clock (OSCCLK)

The P89LPC915/916/917 provides several user-selectable oscillator options in generating

the CPU clock. This allows optimization for a range of needs from high precision to lowest

possible cost. These options are conﬁgured when the ﬂash is programmed and include an

on-chip watchdog oscillator, an on-chip RC oscillator, and an external clock source.

8.3.3 Clock output (P89LPC917)

The P89LPC917 supports a user-selectable clock output function on the CLKOUT pin.

This allows external devices to synchronize to the P89LPC917. This output is enabled by

the ENCLK bit in the TRIM register.

The frequency of this clock output is 1

⁄

2 that of the CCLK. If the clock output is not needed

in Idle mode, it may be turned off prior to entering Idle, saving additional power.

8.4 On-chip RC oscillator option

The P89LPC915/916/917 has a 6-bit TRIM register that can be used to tune the

frequency of the RC oscillator. During reset, the TRIM value is initialized to a factory

pre-programmed value to adjust the oscillator frequency to 7.373 MHz

± 1 % at room

temperature. End-user applications can write to the TRIM register to adjust the on-chip

RC oscillator to other frequencies. If CCLK is 8 MHz or slower, the CLKLP SFR bit

(AUXR1.7) can be set to logic 1 to reduce power consumption. On reset, CLKLP is logic 0

allowing highest performance access. This bit can then be set in software if CCLK is

running at 8 MHz or slower.

8.5 Watchdog oscillator option

The watchdog has a separate oscillator which has a frequency of 400 kHz. This oscillator

can be used to save power when a high clock frequency is not needed.

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