P89LPC915FDH datasheet(39/75 Pages) NXP

39 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

39 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

Some chip functions continue to operate and draw power during Power-down mode,

increasing the total power used during power-down. These include: Brownout detect,

watchdog timer, comparators (note that comparators can be powered down separately),

and RTC/system timer. The internal RC oscillator is disabled unless both the RC oscillator

has been selected as the system clock and the RTC is enabled.

8.15.3 Total Power-down mode

This is the same as Power-down mode except that the brownout detection circuitry and

the voltage comparators are also disabled to conserve additional power. The internal RC

oscillator is disabled unless both the RC oscillator has been selected as the system clock

and the RTC is enabled. If the internal RC oscillator is used to clock the RTC during

power-down, there will be high power consumption. Please use an external low frequency

clock to achieve low power with the RTC running during power-down.

8.16 Reset

The P1.5/RST pin can function as either an active-LOW reset input or as a digital input,

P1.5. The RPE (Reset Pin Enable) bit in UCFG1, when set to ‘1’, enables the external

reset input function on P1.5. When cleared, P1.5 may be used as an input pin.

Remark: During a power-up sequence, the RPE selection is overridden and this pin

always functions as a reset input. An external circuit connected to this pin should not

hold this pin LOW during a power-on sequence as this will keep the device in reset.

After power-up this input will function either as an external reset input or as a digital input

as deﬁned by the RPE bit. Only a power-up reset will temporarily override the selection

deﬁned by RPE bit. Other sources of reset will not override the RPE bit.

Reset can be triggered from the following sources:

• External reset pin (during power-up or if user conﬁgured via UCFG1);

• Power-on detect;

• Brownout detect;

• Watchdog timer;

• Software reset;

• UART break character detect reset.

For every reset source, there is a ﬂag in the Reset Register, RSTSRC. The user can read

this register to determine the most recent reset source. These ﬂag bits can be cleared in

software by writing a ‘0’ to the corresponding bit. More than one ﬂag bit may be set:

• During a power-on reset, both POF and BOF are set but the other ﬂag bits are

cleared.

• For any other reset, previously set ﬂag bits that have not been cleared will remain set.

8.17 Timers/counters 0 and 1

The P89LPC915/916/917 have two general purpose counter/timers which are upward

compatible with the standard 80C51 Timer 0 and Timer 1. Both can be conﬁgured to

operate either as timers or event counters. An option to automatically toggle the T0 and/or

T1 pins upon timer overﬂow has been added.

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