P89LPC915FDH datasheet(36/75 Pages) NXP

36 / 75 page

P89LPC915_916_917_5

Product data sheet

Rev. 05 — 15 December 2009

36 of 75

NXP Semiconductors

P89LPC915/916/917

8-bit microcontrollers with accelerated two-clock 80C51 core

8.13 I/O ports

The P89LPC916 and P89LPC917 devices have three I/O ports: Port 0, Port 1, and Port 2.

The exact number of I/O pins available depends upon the clock and reset options chosen,

as shown in Table 11.

[1]

Required for operation above 12 MHz.

The P89LPC915 has two I/O ports: Port 0 and Port 1. The exact number of I/O pins

available depends upon the clock and reset options chosen, as shown in Table 12.

[1]

Required for operation above 12 MHz.

8.13.1 Port conﬁgurations

All but three I/O port pins on the P89LPC915/916/917 may be conﬁgured by software to

one of four types on a bit-by-bit basis. These are: quasi-bidirectional (standard 80C51 port

outputs), push-pull, open drain, and input-only. Two conﬁguration registers for each port

select the output type for each port pin.

1. P1.5 (RST) can only be an input and cannot be conﬁgured.

2. P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be conﬁgured to be either input-only or

open-drain.

8.13.1.1

Quasi-bidirectional output conﬁguration

Quasi-bidirectional output type can be used as both an input and output without the need

to reconﬁgure the port. This is possible because when the port outputs a logic HIGH, it is

weakly driven, allowing an external device to pull the pin LOW. When the pin is driven

LOW, it is driven strongly and able to sink a fairly large current. These features are

somewhat similar to an open-drain output except that there are three pull-up transistors in

the quasi-bidirectional output that serve different purposes.

Table 11.

Number of I/O pins available (P89LPC916 and P89LPC917)

Clock source

Reset option

Number of I/O

pins (16-pin

package)

RC oscillator or watchdog

oscillator

No external reset (except during

power-up)

External RST pin supported

External clock input

No external reset (except during

power-up)

External RST pin supported[1]

Table 12.

Number of I/O pins available (P89LPC915)

Clock source

Reset option

Number of I/O

pins (14-pin

package)

RC oscillator or watchdog

oscillator

No external reset (except during

power-up)

External RST pin supported

External clock input

No external reset (except during

power-up)

External RST pin supported[1]

P89LPC915FDH датащи(PDF) 36 Page - NXP Semiconductors

P89LPC915FDH датащи(HTML) 36 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75

датащи скачать

ссылки URL