XIO2001 datasheet(99/128 Pages) TI

99 / 128 page

XIO2001

www.ti.com

SCPS212D – MAY 2009 – REVISED JANUARY 2010

5.11 Secondary Uncorrectable Error Mask Register

The secondary uncorrectable error mask register controls the reporting of individual errors as they occur.

When a mask bit is set to 1b, the corresponding error status bit is not set, PCI Express error messages

are blocked, the header log is not loaded, and the first error pointer is not updated. See Table 5-9 for a

complete description of the register contents.

PCI Express extended register offset:

130h

Read-only, Read/Write

Default value:

0000 17A8h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5-9. Secondary Uncorrectable Error Mask Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 00 0000 0000 0000 0000b when read.

13(1)

INTERNAL_ERROR_MASK

Internal bridge error. This mask bit is associated with a PCI-X error and has no effect

on the bridge.

12 (1)

SERR_DETECT_MASK

SERR assertion detected

0 = Error condition is unmasked

1 = Error condition is masked (default)

11 (1)

PERR_DETECT_MASK

PERR assertion detectedi

0 = Error condition is unmasked

1 = Error condition is masked (default)

10 (1)

DISCARD_TIMER_MASK

Delayed transaction discard timer expired

0 = Error condition is unmasked

1 = Error condition is masked (default)

9 (1)

UNCOR_ADDR_MASK

Uncorrectable address error

0 = Error condition is unmasked

1 = Error condition is masked (default)

8 (1)

UNCOR_ATTRIB_MASK

Uncorrectable attribute error. This mask bit is associated with a PCI-X error and has

no effect on the bridge.

7 (1)

UNCOR_DATA_MASK

Uncorrectable data error

0 = Error condition is unmasked

1 = Error condition is masked (default)

6(1)

UNCOR_SPLTMSG_MASK

Uncorrectable split completion message data error. This mask bit is associated with a

PCI-X error and has no effect on the bridge.

5 (1)

SC_ERROR_MASK

Unexpected split completion error. This mask bit is associated with a PCI-X error and

has no effect on the bridge.

RSVD

Reserved. Returns 0b when read.

3 (1)

MASTER_ABORT_MASK

Received master abort

0 = Error condition is unmasked

1 = Error condition is masked (default)

2 (1)

TARGET_ABORT_MASK

Received target abort

0 = Error condition is unmasked

1 = Error condition is masked (default)

1 (1)

MABRT_SPLIT_MASK

Master abort on split completion. This mask bit is associated with a PCI-X error and

has no effect on the bridge.

TABRT_SPLIT_MASK

Target abort on split completion. This mask bit is associated with a PCI-X error and

has no effect on the bridge.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

PCI Express Extended Configuration Space

Submit Documentation Feedback

Product Folder Link(s): XIO2001

XIO2001 датащи(PDF) 99 Page - Texas Instruments

XIO2001 датащи(HTML) 99 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL