XIO2001 datasheet(44/128 Pages) TI

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XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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4.3

Command Register

The command register controls how the bridge behaves on the PCI Express interface. See Table 4-2 for a

complete description of the register contents.

PCI register offset:

04h

Read-only, Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4-2. Command Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

15:11

RSVD

Reserved. Returns 00000b when read.

INTx disable. This bit enables device specific interrupts. Since the bridge does not

INT_DISABLE

generate any internal interrupts, this bit is read-only 0b.

Fast back-to-back enable. The bridge does not generate fast back-to-back transactions;

FBB_ENB

therefore, this bit returns 0b when read.

SERR enable bit. When this bit is set, the bridge can signal fatal and nonfatal errors on the

PCI Express interface on behalf of SERR assertions detected on the PCI bus.

SERR_ENB

0 = Disable the reporting of nonfatal errors and fatal errors (default)

1 = Enable the reporting of nonfatal errors and fatal errors

Address/data stepping control. The bridge does not support address/data stepping, and

STEP_ENB

this bit is hardwired to 0b.

Controls the setting of bit 8 (DATAPAR) in the status register (offset 06h, see Section 4.4)

in response to a received poisoned TLP from PCI Express. A received poisoned TLP is

forwarded with bad parity to conventional PCI regardless of the setting of this bit.

PERR_ENB

0 = Disables the setting of the master data parity error bit (default)

1 = Enables the setting of the master data parity error bit

VGA palette snoop enable. The bridge does not support VGA palette snooping; therefore,

VGA_ENB

this bit returns 0b when read.

Memory write and invalidate enable. When this bit is set, the bridge translates PCI

Express memory write requests into memory write and invalidate transactions on the PCI

interface.

MWI_ENB

0 = Disable the promotion to memory write and invalidate (default)

1 = Enable the promotion to memory write and invalidate

Special cycle enable. The bridge does not respond to special cycle transactions; therefore,

SPECIAL

this bit returns 0b when read.

Bus master enable. When this bit is set, the bridge is enabled to initiate transactions on

the PCI Express interface.

0 = PCI Express interface cannot initiate transactions. The bridge must disable the

MASTER_ENB

response to memory and I/O transactions on the PCI interface (default).

1 = PCI Express interface can initiate transactions. The bridge can forward memory

and I/O transactions from PCI secondary interface to the PCI Express interface.

Memory space enable. Setting this bit enables the bridge to respond to memory

transactions on the PCI Express interface.

0 = PCI Express receiver cannot process downstream memory transactions and must

MEMORY_ENB

respond with an unsupported request (default)

1 = PCI Express receiver can process downstream memory transactions. The bridge

can forward memory transactions to the PCI interface.

I/O space enable. Setting this bit enables the bridge to respond to I/O transactions on the

PCI Express interface.

0 = PCI Express receiver cannot process downstream I/O transactions and must

IO_ENB

respond with an unsupported request (default)

1 = PCI Express receiver can process downstream I/O transactions. The bridge can

forward I/O transactions to the PCI interface.

Classic PCI Configuration Space

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