поискавой системы для электроныых деталей
  Russian  ▼
ALLDATASHEETRU.COM

X  

XIO2001 датащи(PDF) 103 Page - Texas Instruments

Click here to check the latest version.
номер детали XIO2001
подробное описание детали  PCI Express??to PCI Bus Translation Bridge
PDF  128 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
производитель  TI [Texas Instruments]
домашняя страница  http://www.ti.com
Logo TI - Texas Instruments

XIO2001 датащи(HTML) 103 Page - Texas Instruments

Back Button XIO2001 Datasheet HTML 99Page - Texas Instruments XIO2001 Datasheet HTML 100Page - Texas Instruments XIO2001 Datasheet HTML 101Page - Texas Instruments XIO2001 Datasheet HTML 102Page - Texas Instruments XIO2001 Datasheet HTML 103Page - Texas Instruments XIO2001 Datasheet HTML 104Page - Texas Instruments XIO2001 Datasheet HTML 105Page - Texas Instruments XIO2001 Datasheet HTML 106Page - Texas Instruments XIO2001 Datasheet HTML 107Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 103 / 128 page
background image
XIO2001
www.ti.com
SCPS212D – MAY 2009 – REVISED JANUARY 2010
6
Memory-Mapped TI Proprietary Register Space
The programming model of the memory-mapped TI proprietary register space is unique to this device.
All bits marked with a
┦ are sticky bits and are reset by a global reset (GRST) or the internally-generated
power-on reset. All bits marked with a (2) are reset by a PCI Express reset (PERST), a GRST or the
internally-generated power-on reset. The remaining register bits are reset by a PCI Express hot reset,
PERST, GRST, or the internally-generated power-on reset.
Table 6-1. Device Control Memory Window Register Map
REGISTER NAME
OFFSET
Reserved
Revision ID
Device control map ID
000h
Reserved
004h–03Ch
GPIO data(1)
GPIO control (1)
040h
Serial-bus control and status (1)
Serial-bus slave address (1)
Serial-bus word address (1)
Serial-bus data (1)
044h
Serial IRQ edge control(1)
Reserved
Serial IRQ mode
048h
control(1)
Reserved
Serial IRQ status(1)
04Ch
Cache Timer Transfer Limit(1)
PFA Request Limit(1)
050h
Cache Timer Upper Limit(1)
Cache Timer Lower Limit(1)
054h
Reserved
058h–FFFh
(2)
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
(1)
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
6.1
Device Control Map ID Register
The device control map ID register identifies the TI proprietary layout for this device control map. The
value 04h identifies this as a PCI Express-to-PCI bridge.
Device control memory window register offset:
00h
Register type:
Read-only
Default value:
04h
BIT NUMBER
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
1
0
0
Copyright © 2009–2010, Texas Instruments Incorporated
Memory-Mapped TI Proprietary Register Space
103
Submit Documentation Feedback
Product Folder Link(s): XIO2001



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


датащи скачать

Go To PDF Page


ссылки URL



Вашему бизинису помогли Аллдатащит?  [ DONATE ] 

Что такое Аллдатащит   |   реклама   |   контакт   |   Конфиденциальность   |   Ссылка на техническое описание    |   обмен ссыками   |   поиск по производителю
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com