XIO2001 datasheet(40/128 Pages) TI

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XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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If the bridge is the target of a PCI transaction that is forwarded to the PCI Express interface and a data

parity error is detected, then this information is passed to the PCI Express interface. To do this, the bridge

sets the EP bit in the upstream PCI Express header.

3.13 General-Purpose I/O Interface

Up to five general-purpose input/output (GPIO) terminals are provided for system customization. These

GPIO terminals are 3.3-V tolerant.

The exact number of GPIO terminals varies based on implementing the clock run, power override, and

serial EEPROM interface features. These features share four of the five GPIO terminals. When any of the

three shared functions are enabled, the associated GPIO terminal is disabled.

All five GPIO terminals are individually configurable as either inputs or outputs by writing the

corresponding bit in the GPIO control register at offset B4h (See Section 4.59). A GPIO data register at

offset B6h exists to either read the logic state of each GPIO input or to set the logic state of each GPIO

output. The power-up default state for the GPIO control register is input mode.

3.14 Set Slot Power Limit Functionality

The PCI Express Specification provides a method for devices to limit internal functionality and save power

based on the value programmed into the captured slot power limit scale (CSPLS) and capture slot power

limit value (CSPLV) fields of the PCI Express device capabilities register at offset 74h. See Section 4.49,

Device Capabilities Register, for details. The bridge writes these fields when a set slot power limit

message is received on the PCI Express interface.

After the deassertion of PERST, the XIO2001 compares the information within the CSPLS and CSPLV

fields of the device capabilities register to the minimum power scale (MIN_POWER_SCALE) and minimum

power value (MIN_POWER_VALUE) fields in the general control register at offset D4h. See Section 4.65,

General

Control

for

details.

the

CSPLS

and

CSPLV

fields

are

less

than

the

MIN_POWER_SCALE and MIN_POWER_VALUE fields, respectively, then the bridge takes the

appropriate action that is defined below.

The power usage action is programmable within the bridge. The general control register includes a 3-bit

POWER_OVRD field. This field is programmable to the following options:

1. Ignore slot power limit fields.

2. Assert the PWR_OVRD terminal.

3. Disable secondary clocks as specified by the clock mask register at offset D9h (see Section 4.67).

4. Disable secondary clocks as specified by the clock mask register and assert the PWR_OVRD terminal.

5. Respond with unsupported request to all transactions except type 0/1 configuration transactions and

set slot power limit messages

3.15 PCI Express and PCI Bus Power Management

The bridge supports both software-directed power management and active state power management

through standard PCI configuration space. Software-directed registers are located in the power

management capabilities structure located at offset 48h (see Section 4.31). Active state power

management control registers are located in the PCI Express capabilities structure located at offset 70h

(see Section 4.41).

During software-directed power management state changes, the bridge initiates link state transitions to L1

or L2/L3 after a configuration write transaction places the device in a low power state. The power

management state machine is also responsible for gating internal clocks based on the power state.

Table 3-10 identifies the relationship between the D-states and bridge clock operation.

Feature/Protocol Descriptions

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