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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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XIO2001 датащи(PDF) 80 Page - Texas Instruments |
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XIO2001 датащи(HTML) 80 Page - Texas Instruments |
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80 / 128 page  XIO2001 SCPS212D – MAY 2009 – REVISED JANUARY 2010 www.ti.com 4.68 Clock Run Status Register The clock run status register indicates the state of the PCI clock-run features in the bridge. See Table 4-42 for a complete description of the register contents. PCI register offset: DAh Register type: Read-only Default value: 00h BIT NUMBER 7 6 5 4 3 2 1 0 RESET STATE 0 0 0 0 0 0 0 0 Table 4-42. Clock Run Status Register Description BIT FIELD NAME ACCESS DESCRIPTION 7:1 RSVD R Reserved. Returns 000 0000b when read. 0 (1) Secondary clock status. This bit indicates the status of the PCI bus secondary clock outputs. SEC_CLK_STATUS RU 0 = Secondary clock running 1 = Secondary clock stopped (1) These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset. 80 Classic PCI Configuration Space Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): XIO2001 |
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