XIO2001 datasheet(78/128 Pages) TI

78 / 128 page

XIO2001

SCPS212D – MAY 2009 – REVISED JANUARY 2010

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Table 4-39. General Control Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

9:8(1)

MIN_POWER_S

Minimum power scale. This value is programmed to indicate the scale of bits 7:0

CALE

(MIN_POWER_VALUE).

00 = 1.0x

01 = 0.1x

10 = 0.01x (default)

11 = 0.001x

7:0(1)

MIN_POWER_VA

Minimum power value. This value is programmed to indicate the minimum power requirements.

LUE

This value is multiplied by the minimum power scale field (bits 9:8) to determine the minimum

power requirements for the bridge. The default is 5Fh, indicating that the bridge requires 0.95 W

of power. This field can be reprogrammed through an EEPROM or the system BIOS.

4.66 Clock Control Register

This register enables and disables the PCI clock outputs (CLKOUT). See Table 4-40 for a complete

description of the register contents.

PCI register offset:

D8h

Read-only, Read/Write

Default value:

00h

BIT NUMBER

RESET STATE

Table 4-40. Clock Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7(1)

RSVD

Reserved. Returns 0b when read.

6 (1)

Clock output 6 disable. This bit disables secondary CLKOUT6.

CLOCK6_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

5(1)

Clock output 5 disable. This bit disables secondary CLKOUT5.

CLOCK5_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

4(1)

Clock output 4 disable. This bit disables secondary CLKOUT4.

CLOCK4_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

3(1)

Clock output 3 disable. This bit disables secondary CLKOUT3.

CLOCK3_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

2(1)

Clock output 2 disable. This bit disables secondary CLKOUT2.

CLOCK2_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

1(1)

Clock output 1 disable. This bit disables secondary CLKOUT1.

CLOCK1_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

0 (1)

Clock output 0 disable. This bit disables secondary CLKOUT0.

CLOCK0_DISABLE

0 = Clock enabled (default)

1 = Clock disabled

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Classic PCI Configuration Space

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