AD9553SLASHPCBZ datasheet(19/44 Pages) AD

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AD9553

Rev. 0 | Page 19 of 44

THEORY OF OPERATION

A[3:0]

OUTPUT MODE/

SERIAL PORT

PRECONFIGURED

DIVIDER SETTINGS

REFA

XTAL

Y[5:0]

XTAL

VCO

AD9553

OUT1

3350MHz

4050MHz

LOCKED

FILTER

OUT2

SPI CTRL

×2

FDBK

REFERENCE

SWITCHOVER

CONTROL

CLOCK

MUX

CLOCK MUX

HOLD

REF

SEL

DET

SEL REFB

DCXO

CTRL

TEST

RA, ×2A, ÷5A

RB, ×2B, ÷5B

RXO, DCXO CTRL

N, P0, P1, P2

REF SEL

TEST

REF DIFF

REF

DIFF

÷5

÷5A

÷5

÷5B

REFB/REFA

FPFD

PLL

DET

DET A

÷RA

÷N

×2A

×2

DET

DET B

÷RB

×2B

×2

DET

DET XO

÷RXO

RXO

TUNING

CONTROL

UP/2

FPFD/2

FDBK/2

LOCK

DETECT

OUTPUT

MODE

CONTROL

5 OR 6

LOOP

FILTER

CHARGE

PUMP

Figure 20. Detailed Block Diagram

GENERAL DESCRIPTION

The AD9553 can receive up to two input reference clocks, REFA

and REFB. Both input clock paths include an optional divide-

by-5 (/5) prescaler, an optional 2× frequency multiplier, and

a 14-bit programmable divider. Alternatively, the user can

program the device to operate with one differential input clock

(instead of two single-ended input clocks) via the serial I/O

port. In the differential operating mode, the REFB path is

inactive.

The AD9553 also has a dedicated XTAL input for direct

connection of an optional 25 MHz crystal resonator. This allows

for a backup clock signal useful for holdover operation in case

both input references fail. The XTAL clock path includes a fixed

2× frequency multiplier and a 14-bit programmable divider.

The AD9553 includes a switchover control block that auto-

matically handles switching from REFA to REFB (or vice versa)

in the event of a reference failure. If both REFA and REFB fail,

however, then the switchover control block automatically enters

holdover mode by selecting the XTAL clock signal (assuming

the presence of a crystal resonator at the XTAL input).

Generally, the clock signals that appear at the input to the clock

multiplexer (see Figure 20) all operate at the same frequency.

Thus, the frequency at the input to the PLL (FPFD in Figure 20)

is the same regardless of the signal selected by the clock

multiplexer. The PLL converts FPFD to a frequency within the

operating range of the VCO (3.35 GHz to 4.05 GHz) based on

the value of the feedback divider (N). The VCO prescaler (P0)

reduces the VCO output frequency by a factor of either 5 or 6,

resulting in an intermediate frequency in the range of 558 MHz

to 810 MHz. The 10-bit P1 and P2 dividers can further reduce

the P0 output frequency to yield the final output clock frequen-

cies at OUT1 and OUT2, respectively.

Thus, the frequency translation ratio from the reference input

to the output depends on the selection of the /5 prescalers; the

2× frequency multipliers; the values of the three R dividers; the

N divider; and the P0, P1, and P2 dividers. The user can set all

of these parameters automatically by using the preconfigured

divider settings available via the A[3:0] and Y[5:0] pins (see the

Preset Frequencies section). Alternatively, the user can custom

program these parameters via the serial I/O port (see the Serial

Control Port and Register Map sections), allowing the device to

accommodate custom frequency translation ratios.

DESCRIPTION OF FUNCTIONAL BLOCKS

Reference Inputs

The default configuration of the AD9553 provides up to two

single-ended input clock receivers, REFA and REFB, which are

high impedance CMOS inputs. In applications that require

redundant reference clocks with switchover capability, REFA

is the primary reference and REFB the secondary reference.

Alternatively, the user can configure the input (via the serial I/O

port) as a single differential receiver. In this case, the REFB

input functions as REFA (the complementary input of REFA).

Note that in this configuration the device operates with only

one reference input clock, eliminating the need for switchover

functionality.

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