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AD9553/PCBZ датащи(PDF) 40 Page - Analog Devices

номер детали AD9553/PCBZ
подробное описание детали  Flexible Clock Translator for GPON, Base Station, SONET/SDH, T1/E1, and Ethernet
PDF  44 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
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AD9553/PCBZ датащи(HTML) 40 Page - Analog Devices

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AD9553
Rev. 0 | Page 40 of 44
OUT2 Driver Control (Register 0x34)
Table 39.
Address
Bit
Bit Name
Description
0x34
7
OUT2 drive strength
Controls the output drive capability of the OUT2 driver.
0 = weak.
1 = strong (default).
6
OUT2 power-down
Controls power-down functionality of the OUT2 driver.
0 = OUT2 active (default).
1 = OUT2 powered down.
[5:3]
OUT2 mode control
OUT2 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
[2:1]
OUT2 CMOS polarity
Selects the polarity of the OUT2 pins in CMOS mode.
00 = positive pin is normal polarity and negative pin is inverted polarity (default).
01 = positive pin is normal polarity and negative pin is normal polarity.
10 = positive pin is inverted polarity and negative pin logic is inverted polarity.
11 = positive pin logic is inverted polarity and negative pin is normal polarity.
These bits are ineffective unless Bits[5:3] select CMOS mode. See the Output Driver
Polarity (CMOS) section for the definition of normal and inverted polarity.
0
Use Bits[5:3] as source for
OUT2 mode control
Controls OUT2 driver functionality.
0 = OUT2 mode determined by the OM[2:0] pins (default).
1 = OUT2 mode defined by Register 0x34[5:3].



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