AD9553SLASHPCBZ datasheet(18/44 Pages) AD

18 / 44 page

AD9553

Rev. 0 | Page 18 of 44

The SPI/OM[2:0] pins serve double duty (as either SPI pins or

output mode control pins). A mux (controlled by the SPI mode

signal) selects whether the three signals associated with the

SPI/OM[2:0] pins connect to the output mode control decoder

or to the SPI controller. Note that the SPI mode signal

originates from the frequency selection pins decoder.

To enable communication with the SPI controller (SPI

mode), the user must apply the appropriate logic pattern

to the frequency selection pins (A[3:0] = 0000 and/or

Y[5:0] = 000000). Note that as long as the frequency selection

pins are set to invoke SPI mode, the user cannot establish

output mode control via the output mode control decoder.

Conversely, when the frequency selection pins are set to

anything other than SPI mode, the user cannot communicate

with the device via the SPI controller.

In Figure 19, note that some of the functions internal to the

AD9553 are controlled by function bits that originate either

from the two pin decoders or from within the register map.

Specifically, each function receives its function bits from a

function mux; and each function mux, in turn, receives its

control signal from a single enable SPI control bit in the

Be aware that the default values within the register map are such

that all enable SPI control bits are Logic 0. Thus, the default

state of the device is such that each function mux selects the pin

decoders (not the register map) as the source for all control

functions.

In order to switch a function mux so that it selects function

bits from the register map, the user must first set the frequency

selection pins to SPI mode. Then, write a Logic 1 to the appro-

priate enable SPI control bit in the register map. Be aware that

the function mux routes the function bits in the register map

to the selected function the instant that the enable SPI control

bit becomes Logic 1. Thus, it is a good idea to program the

function bits to the desired state prior to writing Logic 1 to

the corresponding enable SPI control bit.

Although the SPI and pin control modes are functionally

independent, it is possible to mix the control modes. For

example, suppose that pin control satisfies all of the require-

ments for an application except for the value of the P2 divider

(which is associated with OUT2). The user could do the

following:

•

Activate SPI mode via the frequency selection pins.

•

Program the desired P0, P1, and P2 values in the register

map (Register 0x15 to Register 0x18).

•

Set the enable SPI control bit for the output dividers

(Register 0x14[2] = 1).

•

Calibrate the VCO by enabling SPI control of VCO

calibration (Register 0x0E[2] = 1), then issue a calibrate

command (Register 0x0E[7] = 1). Be sure to program the

N divider, R dividers, /5 dividers, and ×2 multipliers to the

values defined by the A[3:0] and Y[5:0] pin settings prior

to calibrating the VCO.

•

Restore the original settings to the frequency selection pins

to invoke the desired frequency selection.

In this way, the function muxes that control P0, P1, and P2 select

the appropriate register bits as the source for controlling the

dividers, while all the other function muxes select the pin

decoders as the source for controlling the other functions. Note

that the dividers remain under register control until the user

activates SPI mode and writes Register 0x14[2] = 0, thereby

causing the function mux to use the frequency selection pins

decoder as the source for controlling the dividers, instead of the

AD9553/PCBZ датащи(PDF) 18 Page - Analog Devices

AD9553/PCBZ датащи(HTML) 18 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44

датащи скачать

ссылки URL