AD9553

Rev. 0 | Page 34 of 44

REGISTER MAP DESCRIPTIONS

Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated.

Serial Port Control (Register 0x00 to Register 0x05)

Table 28.

Address

Bit

Bit Name

Description

0x00

7

Unused

Forced to Logic 0 internally, which enables 3-wire mode only.

6

LSB first

Bit order for SPI port.

0 = most significant bit and byte first (default).

1 = least significant bit and byte first.

5

Soft reset

Software initiated reset (register values set to default). This is an autoclearing bit.

4

Unused

Forced to Logic 1 internally, which enables 16-bit mode (the only mode supported by

the device).

[3:0]

Unused

Mirrored version of the contents of Register 0x00[7:4] (that is, Bits[3:0] = Bits[7:4]).

0x04

[7:1]

Unused

Unused.

0

Readback control

For buffered registers, serial port readback reads from actual (active) registers instead of

from the buffer.

0 = reads values currently applied to the internal logic of the device (default).

1 = reads buffered values that take effect on next assertion of I/O update.

0x05

[7:1]

Unused

Unused.

0

I/O update

Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal

control registers of the device. This is an autoclearing bit.

PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)

Table 29.

Address

Bit

Bit Name

Description

0x0A

[7:0]

Charge pump current control

These bits set the magnitude of the PLL charge pump current. The granularity is

~3.5 μA with a full-scale magnitude of ~900 μA. Default is 0x80, or ~448 μA.

Register 0x0A is ineffective unless Register 0x0B[7] = 1.

0x0B

7

Enable SPI control of charge

pump current

Controls the functionality of Register 0x0A.

0 = charge pump current based on A[3:0] and Y[5:0] pins per Table 16 (default).

1 = charge pump current defined by Register 0x0A.

6

Enable SPI control of

antibacklash period

Controls the functionality of Register 0x0D[7:6].

0 = the device automatically controls the antibacklash period (default).

1 = antibacklash period defined by Register 0x0D[7:6].

[5:4]

Charge pump mode

Controls the mode of the PLL charge pump.

00 = tristate.

01 = pump up.

10 = pump down.

11 = normal (default).

3

Disable charge pump

Disables the charge pump (functionally equivalent to Register 0x0B[5:4] = 00).

0 = normal operation (default).

1 = disable charge pump.

2

PFD feedback input edge

control

Selects the polarity of the active edge of the PLL’s feedback input.

0 = positive edge (default).

1 = negative edge.

1

PFD reference input edge

control

Selects the polarity of the active edge of the PLL’s reference input.

0 = positive edge (default).

1 = negative edge.

0

Force VCO to midpoint

frequency

Selects VCO control voltage functionality.

0 = normal VCO operation (default).

1 = force VCO control voltage to midscale.