AD9553SLASHPCBZ datasheet(36/44 Pages) AD

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AD9553

Rev. 0 | Page 36 of 44

PLL and Output Frequency Control (Register 0x11 to Register 0x19)

Table 31.

Address

Bit

Bit Name

Description

0x11

[7:0]

Unused

Unused.

0x12

[7:0]

Feedback divider (N)

Bits[19:12] of the 20-bit feedback divider (N).

0x13

[7:0]

Feedback divider (N)

Bits[11:4] of the 20-bit feedback divider (N).

0x14

[7:4]

Feedback divider (N)

Bits[3:0] of the 20-bit feedback divider (N). Default is N = 0x80000 (524,288).

The feedback divider bits are ineffective unless Register 0x14[3] = 1.

Enable SPI control of

feedback divider

Enables SPI port control of the feedback divider value (N).

0 = The A[3:0] and Y[5:0] pins define N per Table 16 (default).

1 = The 20-bit value in the feedback divider register defines N.

Enable SPI control of

output dividers

Enables SPI port control of the output dividers P0, P1, and P2.

0 = The Y[5:0] pins define the output divider values per

Table 15 (default).

1 = The SPI port registers (0x15, 0x16, 0x18) define the output divider values.

Unused

Unused.

Reset PLL

Controls initialization of the PLL.

0 = normal operation (default).

1 = resets the counters and logic associated with the PLL but does not affect the output dividers.

0x15

[7:0]

P1 divider

Bits[9:2] of the 11-bit P1 divider.

0x16

[7:6]

P1 divider

Bits[1:0] of the 11-bit P1 divider (the default P1 divider register value is 128 decimal).

The P1 divider bits are ineffective unless Register 0x14[2] = 1.

[5:0]

P2 divider

Bits[9:4] of the 11-bit P2 divider.

0x17

[7:4]

P2 divider

Bits[3:0] of the 11-bit P2 divider.

The P2 divider bits are ineffective unless Register 0x14[2] = 1.

Enable test port

Enables use of the LOCKED pin as a test port.

0 = the LOCKED pin indicates PLL status (default).

1 = the LOCKED pin outputs a test signal per Register 0x17[2:1].

[2:1]

Test Mux

Test mux select bits.

00 = crystal oscillator output (XO).

01 = PFD pump up clock divided-by-2 (UP/2).

10 = PFD reference input clock divided-by-2 (FPFD/2).

11 = PFD feedback clock divided-by-2 (FDBK/2).

Unused

Unused.

0x18

Unused

When programming this register write a Logic 0 to this bit.

[6:5]

P0 divider

Sets the P0 divider to divide-by-5 or divide-by-6.

00 = invalid.

01 = divide-by-5.

10 = divide-by-6.

11 = invalid.

The P0 divider bits are ineffective unless Register 0x14[2] = 1.

[4:0]

Unused

Unused.

0x19

[7:0]

Unused

Unused.

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