AD9553SLASHPCBZ datasheet(27/44 Pages) AD

27 / 44 page

AD9553

Rev. 0 | Page 27 of 44

If one chooses fVCO = 3888 MHz, then a possible solution is

R = 1...1,879 (for K = 1/5)

R = 1...3,759 (for K = 2/5)

P0 = 5

R = 2...9,398 (for K = 1)

P1 = 5

R = 3...16,384 (for K = 2)

Relate N, K, and R to the frequency requirements.

N = 3888

R = 125

The two FPFD equations in Step 3 show that fVCO and fREF

relate as

K = 1

FPFD = 1 MHz

If applicable, determine RXO, the XTAL divider value.

REF

VCO

The value of RXO depends on the value of fREF, K, and R

from Step 5, as follows:

Note that fREF is a known quantity (125 MHz) and the VCO

frequencies were determined in Step 2 as 3732.48 MHz and

3888 MHz. Based on these values of fREF and fVCO

125

3888

125

3732

Determine N, K. and R.

For fVCO = 3888 MHz, an obvious solution is K = 1, R = 125

and N = 3888, which satisfies the constraint on both N and

R and yields FPFD = 1 MHz.

For fVCO = 3732.48 MHz, an obvious solution is N = 373,248,

K = 1 and R = 12,500. This choice, however, violates the con-

straints on both N and R in Step 3.

A simple remedy is to divide both N and R by a common factor.

In this particular case, four is the greatest common factor of N

and R. Dividing by four leads to N = 93,312, K = 1, and R =

3,125 (K = 1), satisfying the constraint on N and R, and yielding

FPFD = 40 kHz. Note that to match the values given in the

Preset Frequencies section, FPFD must be 16 kHz. To accom-

plish this, keep R = 3,125, but choose K = 2/5 (see Table 14).

This changes N to 233,280, which agrees with Table 16. In

summary, if one chooses fVCO = 3732.48 MHz, then the solution

set that matches the tables in the Preset Frequencies section is

P0 = 6

P1 = 4

N = 233,280

R = 3,125

K = 2/5

FPFD = 16 kHz

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REF

Given that fREF= 125 MHz, the two results from Step 5 lead to

RXO = 3125 (for R = 3125 and K = 2/5)

RXO = 50 (for R = 125 and K = 1)

LOW DROPOUT (LDO) REGULATORS

The AD9553 is powered from a single 3.3 V supply and contains

on-chip LDO regulators for each function to eliminate the need

for external LDOs. To ensure optimal performance, each LDO

output should have a 0.47 μF capacitor connected between its

access pin and ground.

AUTOMATIC POWER-ON RESET

The AD9553 has an internal power-on reset circuit (see Figure 25).

At power-up, an 800 pF capacitor momentarily holds a Logic 0

at the active low input of the reset circuitry. This ensures that the

device is held in a reset state (~250 μs) until the capacitor charges

sufficiently via the 100 kΩ pull-up resistor and 200 kΩ series

resistor. Note that when using a low impedance source to drive

the RESET pin, be sure that the source is either tristate or Logic 0

at power-up. Otherwise, the device may not calibrate properly.

RESET

200k

Ω

100k

Ω

800pF

VDD

AD9553

RESET

CIRCUITRY

Figure 25. Power-On Reset

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