AD9553SLASHPCBZ datasheet(14/44 Pages) AD

14 / 44 page

AD9553

Rev. 0 | Page 14 of 44

PRESET FREQUENCIES

The frequency selection pins (A[3:0] and Y[5:0]) allow the user

to hardwire the device for preset input and output frequencies

based on the pin logic states (see Figure 20). The pins decode

ground or open connections as Logic 0 or Logic 1, respectively.

In order to have access to the device control registers via the SPI

port, the user must select Y[5:0] = 000000 and/or A[3:0] = 0000.

Doing so causes Pin 12 through Pin 14 to function as SPI port

control pins instead of output mode control pins (see the Output

Driver Mode Control section). Note that after selecting SPI

mode, the user must write a Logic 1 to Bit 0 of Register 0x32 and

OUT2 mode control bits (see Figure 23 and the Output Driver

Mode Control section).

The A[3:0] pins allow the user to select one of fifteen input

reference frequencies as shown in Table 14. The device sets the

appropriate divide-by-5 (/5A, /5B), multiply-by-2 (×2A, ×2B),

and input divider (RA, RB, RXO) values based on the logic levels

applied to the A[3:0] pins.

The same settings apply to both the REFA and REFB input

paths. Furthermore, the /5, ×2, and R values cause the PLL

input frequency to be either 16 kHz or 40/3 kHz. The excep-

tions are A[3:0] = 1101 and 1110, which yield a PLL input

frequency of 155.52/59 MHz and 4.86 MHz, respectively.

Note that the XTAL input is not available for holdover

functionality in the A[3:0] = 1101 and 1110 configurations,

thus the undefined RXO value.

The Y[5:0] pins allow the user to select one of 51 output

frequency combinations (fOUT1 and fOUT2) per Table 15.

The device sets the appropriate P0, P1, and P2 settings based

on the logic levels applied to the Y[5:0] pins. Note, however,

that selections 101101 through 110010 require A[3:0] = 1101

and selection 110011 requires A[3:0] = 1110.

The value (N) of the PLL feedback divider and the control

setting for the charge pump current (CP) depend on a

combination of both the A[3:0] and Y[5:0] pin settings as

shown in Table 16.

Table 14. Pin-Configured Input Frequency1

Pins A[3:0]

fREFA, fREFB (MHz)

/5A, /5B

×2A, ×2B

RA, RB (Decimal)

RXO (Decimal)

0000

SPI mode

0001

0.008

–

3125

0010

1.536

–

3125

0011

2.048

–

128

3125

0100

16.384

–

1024

3125

0101

19.44

–

1215

3125

0110

–

3125

0111

38.88

–

2430

3125

1000

61.44

–

3840

3125

1001

77.76

–

4860

3125

1010

122.88

–

7680

3125

1011

125

3125

1100

1.544

–

193

3125

11012

155.52

–

Undefined

11103

77.76

–

Undefined

1111

200/3

–

5000

3750

1 For /5 and ×2 frequency scalers, – indicates bypassed and On indicates active.

2 Pins A[3:0] = 1101 only works with Pins Y[5:0] =101101 through 110010.

3 Pins A[3:0] = 1110 only works with Pins Y[5:0] =110011.

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