UPSD3233 datasheet(128/170 Pages) STMICROELECTRONICS

128 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

128/170

POWER MANAGEMENT

All PSD Modules offer configurable power saving

options. These options may be used individually or

in combinations, as follows:

–

The primary and secondary Flash memory,

and SRAM blocks are built with power

management technology. In addition to using

special silicon design methodology, power

management technology puts the memories

into Standby Mode when address/data inputs

are not changing (zero DC current). As soon

as a transition occurs on an input, the affected

memory “wakes up,” changes and latches its

outputs, then goes back to standby. The

designer does

not have to do anything special

to achieve Memory Standby Mode when no

inputs are changing—it happens

automatically.

–

The PLD sections can also achieve Standby

Mode when its inputs are not changing, as

described in the sections on the Power

Management Mode Registers (PMMR).

–

As with the Power Management Mode, the

Automatic Power Down (APD) block allows

the PSD Module to reduce to stand-by current

automatically. The APD Unit can also block

MCU address/data signals from reaching the

memories and PLDs.

–

Built in logic monitors the Address Strobe of

the MCU for activity. If there is no activity for a

certain time period (MCU is asleep), the APD

Unit initiates Power-down Mode (if enabled).

Once in Power-down Mode, all address/data

signals are blocked from reaching memory

and PLDs, and the memories are deselected

internally. This allows the memory and PLDs

to remain in Standby Mode even if the

address/data signals are changing state

externally (noise, other devices on the MCU

bus, etc.). Keep in mind that any unblocked

PLD input signals that are changing states

keeps the PLD out of Stand-by Mode, but not

the memories.

–

PSD Chip Select Input (CSI, PD2) can be

used to disable the internal memories, placing

them in Standby Mode even if inputs are

changing. This feature does not block any

internal signals or disable the PLDs. This is a

good alternative to using the APD Unit. There

is a slight penalty in memory access time

when PSD Chip Select Input (CSI, PD2)

makes its initial transition from deselected to

selected.

–

The PMMRs can be written by the MCU at run-

time to manage power. The PSD Module

supports “blocking bits” in these registers that

are set to block designated signals from

reaching both PLDs. Current consumption of

the PLDs is directly related to the composite

frequency of the changes on their inputs (see

Figure 72 and Figure 73., page 135).

Significant power savings can be achieved by

blocking signals that are not used in DPLD or

CPLD logic equations.

Figure 69. APD Unit

APD EN

PMMR0 BIT 1=1

ALE

RESET

CSI

CLKIN

TRANSITION

DETECTION

EDGE

DETECT

APD

COUNTER

POWER DOWN

(PDN)

DISABLE BUS

INTERFACE

CSIOP SELECT

FLASH SELECT

SRAM SELECT

CLR

DISABLE

FLASH/SRAM

PLD

SELECT

AI06608

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