UPSD3233 datasheet(116/170 Pages) STMICROELECTRONICS

116 / 170 page

uPSD3234A, uPSD3234BV, uPSD3233B, uPSD3233BV

116/170

Output Macrocell (OMC)

Eight of the Output Macrocells (OMC) are con-

nected to Ports A and B pins and are named as

McellAB0-McellAB7. The other eight macrocells

are connected to Ports B and C pins and are

named as McellBC0-McellBC7. If an McellAB out-

put is not assigned to a specific pin in PSDsoft, the

Macrocell Allocator block assigns it to either Port A

or B. The same is true for a McellBC output on Port

B or C. Table 91 shows the macrocells and port

assignment.

The Output Macrocell (OMC) architecture is

shown in Figure 61., page 117. As shown in the

figure, there are native product terms available

from the AND Array, and borrowed product terms

available (if unused) from other Output Macrocells

(OMC). The polarity of the product term is con-

trolled by the XOR gate. The Output Macrocell

(OMC) can implement either sequential logic, us-

ing the flip-flop element, or combinatorial logic.

The multiplexer selects between the sequential or

combinatorial logic outputs. The multiplexer output

can drive a port pin and has a feedback path to the

AND Array inputs.

The flip-flop in the Output Macrocell (OMC) block

can be configured as a D, T, JK, or SR type in PS-

Dsoft. The flip-flop’s clock, preset, and clear inputs

may be driven from a product term of the AND Ar-

ray. Alternatively, CLKIN (PD1) can be used for

the clock input to the flip-flop. The flip-flop is

clocked on the rising edge of CLKIN (PD1). The

preset and clear are active High inputs. Each clear

input can use up to two product terms.

Table 91. Output Macrocell Port and Data Bit Assignments

Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package.

2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs.

Output

Macrocell

Port

Assignment(1,2)

Native Product Terms

Maximum Borrowed

Product Terms

Data Bit for Loading or

Reading

McellAB0

Port A0, B0

McellAB1

Port A1, B1

McellAB2

Port A2, B2

McellAB3

Port A3, B3

McellAB4

Port A4, B4

McellAB5

Port A5, B5

McellAB6

Port A6, B6

McellAB7

Port A7, B7

McellBC0

Port B0

McellBC1

Port B1

McellBC2

Port B2, C2

McellBC3

Port B3, C3

McellBC4

Port B4, C4

McellBC5

Port B5

McellBC6

Port B6

McellBC7

Port B7, C7

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