AD9992BBCZ datasheet(30/92 Pages) AD

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AD9992

Rev. C | Page 30 of 92

Table 14. Summary of V-Sequence Registers (see Table 10 and Table 11 for the CLPOB, PBLK, and HBLK Pattern Register

Length

Description

HOLD

Use in conjunction with VMASK_EN.

1: HOLD function instead of FREEZE/RESUME function.

VMASK_EN

Enables the masking of XV1 to XV24 outputs at the locations specified by the FREEZE/RESUME registers.

1: Enable masking for all groups. One bit for each set of Freeze and Resume Positions 1 to 4.

CONCAT_GRP

Combines toggle positions of Groups A/B/C/D when enabled. Only Group A settings for start, polarity, length,

and repetition are used when this mode is selected.

0: Disable.

1: Enable the addition of all toggle positions from VPATSELA/B/C/D.

2: Test mode only. Do not use.

…

15: Test mode only. Do not use.

VREP_MODE

Selects line alternation for V-output repetitions. Note separate controls for Group A and Groups B/C/D.

0: Disable alternation. Group A uses VREPA_1, Groups B/C/D use VREP _EVEN for all lines.

1: 2-line. Group A alternates VREPA_1 and VREPA_2. Groups B/C/D alternate VREP_EVEN and VREP_ODD.

2: 3-line. Group A alternates VREPA_1, VREPA_2, and VREPA_3. Groups B/C/D follow a VREP_EVEN, VREP_ODD,

VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern.

3: 4-line. Group A alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation.

LASTREPLEN_EN

Enables a separate pattern length to be used during the last repetition of the V-sequence. One bit for

each group (A, B, C, and D). Set bit high to enable. Group A is the LSB. Recommended value is enabled.

LASTTOG_EN

Enables a final toggle position to be added at the end of the V-sequence. The toggle position is shared

by all V-outputs in the same group. One bit for each group. Set bit high to enable. Group A is the LSB.

HDLENE

13b

HD line length for even lines in the V-sequence.

HDLENO

13b

HD line length for odd lines in the V-sequence.

VPOL_A

24b

Group A start polarity bits for each XV1 to XV24 output.

VPOL_B

24b

Group B start polarity bits for each XV1 to XV24 output.

VPOL_C

24b

Group C start polarity bits for each XV1 to XV24 output.

VPOL_D

24b

Group D start polarity bits for each XV1 to XV24 output.

GROUPSEL_0

24b

Assigns each XV1 to XV12 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV1, Bits

[3:2] are for XV2 … Bits [23:22] are for XV12.

0: Assign to Group A

1: Assign to Group B

2: Assign to Group C

3: Assign to Group D

GROUPSEL_1

24b

Assigns each XV13 to XV24 output to either Group A/B/C/D. Two bits for each signal. Bits [1:0] are for XV13,

Bits [3:2] are for XV14 … Bits [23:22] are for XV24.

0: Assign to Group A.

1: Assign to Group B.

2: Assign to Group C.

3: Assign to Group D.

VPATSELA

Selected V-pattern for Group A.

VPATSELB

Selected V-pattern for Group B.

VPATSELC

Selected V-pattern for Group C.

VPATSELD

Selected V-pattern for Group D.

VSTARTA

13b

Start position for the selected V-Pattern Group A.

VSTARTB

13b

Start position for the selected V-Pattern Group B.

VSTARTC

13b

Start position for the selected V-Pattern Group C.

VSTARTD

13b

Start position for the selected V-Pattern Group D.

VLENA

13b

Length of selected V-Pattern Group A.

VLENB

13b

Length of selected V-Pattern Group B.

VLENC

13b

Length of selected V-Pattern Group C.

VLEND

13b

Length of selected V-Pattern Group D.

VREPA_1

13b

Number of repetitions for the V-Pattern Group A for first lines (even).

VREPA_2

13b

Number of repetitions for the V-Pattern Group A for second lines (odd).

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