AD9992BBCZ datasheet(62/92 Pages) AD

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AD9992

Rev. C | Page 62 of 92

ANALOG FRONT END DESCRIPTION AND OPERATION

6dB ~ 42dB

CCDIN

CLI

DIGITAL

FILTER

CLPOB

DC RESTORE

OPTICAL BLACK

CLAMP

12-BIT

ADC

VGA

DAC

CDS

INTERNAL

VREF

2V FULL SCALE

PRECISION

TIMING

GENERATION

SHP

SHD

1.2V

OUTPUT

DATA

LATCH

REFT

REFB

V-H

TIMING

GENERATION

SHP SHD

DOUTPHASE

CLPOB PBLK

0.4V

1.4V

AD9992

0.1µF

VGA GAIN

0.1µF 0.1µF

CLAMP LEVEL

PBLK

–3dB, 0dB,

+3dB, +6dB

PBLK

PBLK (WHEN DCBYP = 1)

SHP

S11

S21

BLANK TO

ZERO OR

CLAMP LEVEL

1S1 IS NORMALLY CLOSED; S2 IS NORMALLY OPEN.

CDS GAIN

DOUT

DOUTPHASE

DCLK

MODE

FIXED

DELAY

CLI

DCLKINV

Figure 72. Analog Front-End Functional Block Diagram

The AD9992 signal processing chain is shown in Figure 72.

Each processing step is essential for achieving a high quality

image from the raw CCD pixel data.

DC Restore

To reduce the large dc offset of the CCD output signal, a dc

restore circuit is used with an external 0.1 μF series coupling

capacitor. This restores the dc level of the CCD signal to

approximately 1.2 V, making it compatible with the 1.8 V core

supply voltage of the AD9992. The dc restore switch is active

during the SHP sample pulse time.

The dc restore circuit can be disabled when the optional PBLK

signal is used to isolate large-signal swings from the CCD input

(see the Analog Preblanking section). Bit 6 of AFE Register

Address 0x00 controls whether the dc restore is active during the

PBLK interval.

Analog Preblanking

During certain CCD blanking or substrate clocking intervals,

the CCD input signal to the AD9992 can increase in amplitude

beyond the recommended input range. The PBLK signal can be

used to isolate the CDS input from large-signal swings. While

PBLK is active (low), the CDS input is internally shorted to ground.

Note that, because the CDS input is shorted during PBLK, the

CLPOB pulse should not be used during the same active time as

the PBLK pulse.

Correlated Double Sampler (CDS)

The CDS circuit samples each CCD pixel twice to extract the video

information and to reject low frequency noise. The timing

shown in Figure 19 illustrates how the two internally generated

CDS clocks, SHP and SHD, are used to sample the reference

level and data level of the CCD signal, respectively. The placement

of the SHP and SHD sampling edges is determined by the setting

of the SHPLOC and SHDLOC registers located at Address 0x37.

Placement of these two clock signals is critical for achieving the

best performance from the CCD.

The CDS gain is variable in three steps by using the AFE

Address 0x04: −3 dB, 0 dB (default), and +3 dB. Improved noise

performance results from using the +3 dB setting, but the input

range is reduced (see the Analog Specifications section).

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