AD9992BBCZ datasheet(17/92 Pages) AD

17 / 92 page

AD9992

Rev. C | Page 17 of 92

H1 TO H8 PROGRAMMABLE EDGES:

1H1 RISING EDGE.

2H1 FALLING EDGE.

3H5 RISING EDGE.

4H5 FALLING EDGE.

H1, H3

H2, H4

H5, H7

H6, H8

Figure 18. HCLK Mode 3 Operation

CCD

SIGNAL

CLI

SHP

SHD

DOUTPHASEP

POSITION

NOTES:

1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.

TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.

2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.

3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.

4. THE tSHPINH AREA FROM 50 TO 62 ONLY APPLIES IN SLAVE MODE.

5. THE tSHDINH AREA WLL APPLY TO EITHER H1 RISING OR FALLING EDGE, DEPENDING ON THE VALUE OF THE

H1HBLK MASKING POLARITY.

6. THE tSHDINH AREA CAN ALSO BE CHANGED TO A tSHPINH AREA IF THE H1HBLKRETIME BIT = 1.

P[0]

P[64] = P[0]

P[32]

P[16]

P[48]

RGr[0]

RGf[16]

SHDLOC[0]

H1r[0]

H1f[32]

SHPLOC[32]

tDOUTINH

tSHDINH

tSHPINH

tSHDINH

tS2

tS1

Figure 19. High Speed Timing Default Locations

Digital Data Outputs

The AD9992 data output and DCLK phase are programmable

using the DOUTPHASE registers (Address 0x38, Bits [11:0]).

DOUTPHASEP (Bits [5:0]) selects any edge location from 0 to

63, as shown in Figure 20. DOUTPHASEN (Bits [11:6]) does

not actually program the phase of the data outputs but is used

internally and should always be programmed to a value of

DOUTPHASEP plus 32 edges. For example, if DOUTPHASEP

is set to 0, DOUTPHASEN should be set to 32 (0x20).

Normally, the DOUT and DCLK signals track in phase, based

on the contents of the DOUTPHASE registers. The DCLK output

phase can also be held fixed with respect to the data outputs by

changing the DCLKMODE register high (Address 0x38, Bit 12). In

this mode, the DCLK output remains at a fixed phase equal to a

delayed version of CLI while the data output phase is still

programmable.

The pipeline delay through the AD9992 is shown in Figure 21.

After the CCD input is sampled by SHD, there is a 16-cycle

delay until the data is available.

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