AD9992BBCZ datasheet(76/92 Pages) AD

76 / 92 page

AD9992

Rev. C | Page 76 of 92

Address

Data

Bits

Default

Value

Update

Type

Mnemonic

Description

[2]

SYNCSUSPEND

Suspend clocks during SYNC active pulse:

0: Do not suspend.

1: Suspend.

[3]

ENH_SYNC_EN

1: Enable enhanced sync/shutter operations.

[4]

SYNC_MASK_HD

1: Mask HD during SYNCSUSPEND.

[5]

SYNC_MASK_VD

1: Mask VD during SYNCSUSPEND.

[6]

SYNC_MASK_V

1: Mask XV outputs during SYNCSUSPEND.

[7]

SHADOW_EN

1: Enable use of shadow registers.

[12:8]

TEST

Test mode only. Must be set to 0.

[13]

UPDATE_SHADOW

1: Writes to shadow bits affect shadow registers, not

primary.

[14]

SWSYNC

1: Initiate software SYNC event (self-clears to 0 after SYNC).

0x14

[0]

SCK

TGCORE_RSTB

Timing core reset bar. 0: reset TG core;

1: resume operation.

0x15

[0]

SCK

OSC_RSTB

CLO oscillator reset bar:

0: Oscillator in power-down state.

1: Resume oscillator operation.

0x16

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

0x17

[12:0]

SCK

UPDATE

Serial update line.

Sets the line (HD) within the field to update the VD-updated

registers.

[13]

PREVENTUP

Prevents the update of the VD-updated registers:

0: Normal update.

1: Prevent update of VD-updated registers.

[14]

SYNC_RST_SHUTEN

1: Enable reset of the shutter control after SYNC operation

occurs.

[15]

REG_RST_SHUT

1: Forces shutter control to reset.

[16]

GPO_RST_SYNC

1: Reset shutter and GPO control at SYNC operation.

[17]

GPO_LINE_COUNT_OFFSET

0: First line in a field is considered Line 1 for GPOs.

1: First line in a field is considered Line 0 for GPOs.

0x18

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

0x19

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

0x1A

[27:0]

SCK

TEST

Test mode only. Must be set to 0.

0x1B

[27:0]

SCK

TEST

Test mode only. Must be set to 0xA.

0x1C

[23:0]

FF0000

SCK

VSGSELECT

Each bit selects XV pulses for use as VSG pulses.

0x1D

[23:0]

SCK

VSGMASK_CTL

VSG masking. Overrides settings in field registers when

enabled.

[24]

VSGMASK_CTL_EN

0: Disable VSGMAK_CTL bits. VSG masking is controlled by

field registers.

1: Enable VSGMASK_CTL bits to control VSG masking.

0x1F

[0]

SCK

HCNT14_EN

1: Enable 14-bit H-counter.

[1]

PBLK_MASK_EN

1: Disable clamp operation if PBLK is active at the same time

as CLPOB.

Table 31. VD/HD Registers

Address

Data

Bits

Default

Value

Update

Type

Mnemonic

Description

0x20

[0]

SCK

MASTER

VD/HD master or slave mode:

0: Slave mode.

1: Master mode.

0x21

[0]

VDHDPOL

VD/HD active polarity:

0: Low.

1: High.

0x22

[12:0]

HDRISE

Rising edge location for HD. Minimum value is 36 pixels.

[25:13]

VDRISE

Rising edge location for VD.

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