7641 datasheet(33/385 Pages) RENESAS

33 / 385 page

Rev.2.00

Aug 28, 2006

page 16 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION

Table 6 List of I/O port function

Name

Port P0

Port P1

Port P2

Input/Output

Input/Output,

individual bits

I/O format

CMOS input level

CMOS 3-state output

Non-port function

Lower address

output

Higher address

output

Data bus I/O

Related SFRs

CPU mode register A

Port control register

Ref. No.

(1)

P00/AB0–

P07/AB7

P10/AB8–

P17/AB15

P20/DB0–

P27/DB7

P60/DQ0–

P67/DQ7

(2)

CPU mode register A

Port control register

Port P2 pull-up control

CPU mode register A

CPU mode register B

Port control register

CPU mode register A

CPU mode register B

Port control register

Timer X mode register

Timer Y mode register

Interrupt polarity select register

CPU mode register A

Port control register

Clock control register

Timer 123 mode register

Data bus buffer control

Port control register

Control signal I/O

CMOS input level/VIHL

input level

CMOS 3-state output

Port P3

(1)

(3)

(4)

(5)

CMOS input level

CMOS 3-state output

P30/RDY–

P37/RD

P40/EDMA,

Port P4

P41/INT0,

P42/INT1,

P43/CNTR0,

P44/CNTR1

Control signal I/O

External interrupt

P50/XCIN,

P51/TOUT/

XCOUT

CMOS input level

CMOS 3-state output

(6)

(7)

Timer 1, Timer 2

output pin

Sub-clock generat-

ing input pin

P52/OBF0,

P53/IBF0,

P54/S0,

P55/A0,

P56/R(E),

P57/W(R/W)

Port P5

CMOS input level

CMOS 3-state output

CMOS input level/TTL

input level in Master

CPU bus inferface

function

(8)

(9)

(10)

CMOS input level/TTL

input level

CMOS 3-state output

CMOS input level

CMOS 3-state output

CMOS input level

CMOS 3-state output

CMOS input level/TTL

input level in Master

CPU bus inferface

function

CMOS input level

CMOS 3-state output

(11)

Data bus buffer control

Port control register

USB control register

Port control register

Data bus buffer control

Port control register

CPU mode register B

P70/SOF,

Port P6

Port P7

P71/HOLD,

P72/S1,

P73/IBF1/

HLDA,

P74/OBF1

(12)

(13)

(14)

(15)

(16)

Master CPU bus

interface I/O pin

Master CPU bus

interface I/O pin

USB function output

Control signal I/O

Master CPU bus

interface I/O pin

(17)

(18)

(19)

(20)

(21)

(22)

(23)

(24)

UART1, 2 control registers

Serial I/O control register 1

Serial I/O control register 2

Port control register

Serial I/O I/O pin

UART2 I/O pin

UART1 I/O pin

P80/UTXD2/

SRDY,

P81/URXD2/

SCLK,

P82/CTS2/

SRXD,

P83/RTS2/

STXD,

P84/UTXD1,

P85/URXD1,

P86/CTS1,

P87/RTS1

Port P8

Notes 1: For details of the ports functions in modes other than single-chip mode, and how to use double-function ports as function I/O ports, refer to the applicable

sections.

2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.

When an input level is at an intermediate potential, a rush current will flow from VCC to VSS through the input-stage gate.

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