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7641 датащи(PDF) 73 Page - Renesas Technology Corp |
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7641 датащи(HTML) 73 Page - Renesas Technology Corp |
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73 / 385 page ![]() Rev.2.00 Aug 28, 2006 page 56 of 113 7641 Group REJ09B0336-0200 HARDWARE FUNCTIONAL DESCRIPTION [USB Endpoint x (x = 1 to 4) OUT Control Register] OUT_CSR This register contains the information and status of the respective OUT endpoints 1 to 4. In the endpoint 0, all bits are reserved and cannot be used (they will all be read out as “0”). The USB FCU sets the OUT_PKT_RDY flag to “1” after a data packet has been received into the OUT FIFO. After reading the data packet in the OUT FIFO, clear this flag to “0”. However, if there is still data in the OUT FIFO, the flag cannot be cleared even by writing “0” by soft- ware. USB endpoint x OUT control register (address 005A16) OUT_CSR OUT_PKT_RDY flag (OUTXCSR0) 0: Except the following condition (Note 3) 1: End of a data packet reception (Note 2) OVER RUN flag (OUTXCSR1) (In isochronous data transfer) 0: No FIFO overrun (Note 2) 1: FIFO overrun occurred (Note 1) SEND_STALL bit (OUTXCSR2) (Note 2) 0: Except the following condition 1: Transmitting STALL handshake signal ISO/TOGGLE_INIT bit (OUTXCSR3) (Note 2) 0: Except the following condition 1: Initializing to endpoint used for isochronous transfer; Enabling reception of DATA0 and DATA1 as PID (Initializing the toggle) FORCE_STALL flag (OUTXCSR4) 0: Except the following condition (Note 2) 1: Protocol error detected (Note 1) DATA_ERR flag (OUTXCSR5) 0: Except the following condition (Note 2) 1: CRC or bit stuffing error detected in transferring isochronous data (Note 1) FLUSH bit (OUTXCSR6) 0: Except the following condition (Note 1) 1: Flush FIFO. (Note 2) AUTO_CLR bit (OUTXCSR7) (Note 2) 0: AUTO_CLR disabled 1: AUTO_CLR enabled b0 b7 Notes 1: This bit is automatically set to “1” or cleared to “0”. 2: The user must program to “1” or “0”. 3: When AUTO_CLR bit is “0”, the user must clear to “0”. When AUTO_CLR bit is “1”, this bit is automatically cleared to “0”. Fig. 48 Structure of USB endpoint x (x = 1 to 4) OUT control register |
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