7641 datasheet(14/385 Pages) RENESAS

14 / 385 page

Rev.2.00

Aug 28, 2006

page 10 of 13

7641 Group

REJ09B0336-0200

Fig. 3.5.10 Structure of Port P4, Port P7 .................................................................................... 53

Fig. 3.5.11 Structure of Port Pi direction register ...................................................................... 54

Fig. 3.5.12 Structure of Port P4, Port P7 direction registers ................................................... 54

Fig. 3.5.13 Structure of Port control register .............................................................................. 55

Fig. 3.5.14 Structure of Interrupt polarity select register .......................................................... 55

Fig. 3.5.15 Structure of Port P2 pull-up control register ........................................................... 56

Fig. 3.5.16 Structure of USB control register ............................................................................. 56

Fig. 3.5.17 Structure of Clock control register ............................................................................ 57

Fig. 3.5.18 Structure of Timer X ................................................................................................... 57

Fig. 3.5.19 Structure of Timer Y ................................................................................................... 58

Fig. 3.5.20 Structure of Timer i .................................................................................................... 58

Fig. 3.5.21 Structure of Timer X mode register ......................................................................... 59

Fig. 3.5.22 Structure of Timer Y mode register ......................................................................... 60

Fig. 3.5.23 Structure of Timer 123 mode register ...................................................................... 61

Fig. 3.5.24 Structure of Serial I/O shift register ......................................................................... 61

Fig. 3.5.25 Structure of Serial I/O control register 1 ................................................................. 62

Fig. 3.5.26 Structure of Serial I/O control register 2 ................................................................. 62

Fig. 3.5.27 Structure of Special count source generator 1 ....................................................... 63

Fig. 3.5.28 Structure of Special count source generator 2 ....................................................... 63

Fig. 3.5.29 Structure of Special count source mode register ................................................... 64

Fig. 3.5.30 Structure of UARTx (x = 1, 2) mode register ......................................................... 64

Fig. 3.5.31 Structure of UARTx (x = 1, 2) baud rate generator .............................................. 65

Fig. 3.5.32 Structure of UARTx (x = 1, 2) status register ........................................................ 65

Fig. 3.5.33 Structure of UARTx (x = 1, 2) control register ....................................................... 66

Fig. 3.5.34 Structure of UARTx (x = 1, 2) transmit/receive buffer registers 1, 2 ................. 67

Fig. 3.5.35 Structure of UARTx (x = 1, 2) RTS control register .............................................. 68

Fig. 3.5.36 Structure of DMAC index and status register ......................................................... 69

Fig. 3.5.37 Structure of DMAC channel x (x = 0, 1) mode register 1 .................................... 70

Fig. 3.5.38 Structure of DMAC channel 0 mode register 2 ...................................................... 71

Fig. 3.5.39 Structure of DMAC channel 1 mode register 2 ...................................................... 72

Fig. 3.5.40 Structure of DMAC channel x (x = 0, 1) source registers Low, High ................. 73

Fig. 3.5.41 Structure of DMAC channel x (x = 0, 1) destination registers Low, High ......... 73

Fig. 3.5.42 Structure of DMAC channel x (x = 0, 1) transfer count registers Low, High .... 74

Fig. 3.5.43 Structure of Data bus buffer register x (x = 0, 1) ................................................. 75

Fig. 3.5.44 Structure of Data bus buffer status register x (x = 0, 1) ..................................... 75

Fig. 3.5.45 Structure of Data bus buffer control register 0 ...................................................... 76

Fig. 3.5.46 Structure of Data bus buffer control register 1 ...................................................... 76

Fig. 3.5.47 Structure of USB address register ........................................................................... 77

Fig. 3.5.48 Structure of USB power management register ....................................................... 77

Fig. 3.5.49 Structure of USB interrupt status register 1 ........................................................... 78

Fig. 3.5.50 Structure of USB interrupt status register 2 ........................................................... 79

Fig. 3.5.51 Structure of USB interrupt enable register 1 .......................................................... 80

Fig. 3.5.52 Structure of USB interrupt enable register 2 .......................................................... 80

Fig. 3.5.53 Structure of USB frame nmber registers Low, High .............................................. 81

Fig. 3.5.54 Structure of USB endpoint index register ................................................................ 82

Fig. 3.5.55 Structure of USB endpoint x (x = 0 to 4) IN control register .............................. 83

Fig. 3.5.56 Structure of USB endpoint x (x = 1 to 4) OUT control register .......................... 84

Fig. 3.5.57 Structure of USB endpoint x (x = 0 to 4) IN max. packet size register ............ 84

Fig. 3.5.58 Structure of USB endpoint x (x = 0 to 4) OUT max. packet size register ........ 85

Fig. 3.5.59 Structure of USB endpoint x (x = 0 to 4) OUT write count registers Low, High

...................................................................................................................................... 86

List of figures

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