7641 datasheet(10/385 Pages) RENESAS

10 / 385 page

Rev.2.00

Aug 28, 2006

page 6 of 13

7641 Group

REJ09B0336-0200

Fig. 97 Timing for Boot ROM area output ................................................................................ 102

Fig. 98 Timing for ID check ......................................................................................................... 103

Fig. 99 ID code storage addresses ............................................................................................ 103

Fig. 100 Full status check flowchart and remedial procedure for errors .............................. 106

Fig. 101 Example circuit application for standard serial I/O mode ........................................ 107

Fig. 102 Passive components near LPF pin ............................................................................. 111

Fig. 103 Peripheral circuit ............................................................................................................ 111

Fig. 104 Timing chart after interrupt occurs .............................................................................. 113

Fig. 105 Time up to execution of interrupt processing routine .............................................. 113

CHAPTER 2 APPLICATION

Fig. 2.1.1 Memory map of registers related to I/O port .............................................................. 2

Fig. 2.1.2 Structure of Port Pi register .......................................................................................... 3

Fig. 2.1.3 Structure of Port P4, Port P7 registers ....................................................................... 3

Fig. 2.1.4 Structure of Port Pi direction register (i = 0, 1, 2, 3, 5, 6, 8) ................................. 4

Fig. 2.1.5 Structure of Port P4 direction, Port P7 direction registers ....................................... 4

Fig. 2.1.6 Structure of Port control register .................................................................................. 5

Fig. 2.1.7 Structure of Port P2 pull-up control register ............................................................... 5

Fig. 2.1.8 Structure of Interrupt request register C ..................................................................... 6

Fig. 2.1.9 Structure of Interrupt control register C ....................................................................... 6

Fig. 2.1.10 Registers setting ............................................................................................................ 7

Fig. 2.1.11 Connection diagram ...................................................................................................... 8

Fig. 2.1.12 Control procedure .......................................................................................................... 8

Fig. 2.2.1 Memory map of registers relevant to timers ............................................................. 12

Fig. 2.2.2 Structure of Timer i (i=1, 2, 3) .................................................................................... 13

Fig. 2.2.3 Structure of Timer 123 mode register ........................................................................ 13

Fig. 2.2.4 Structure of Timer X (low-order, high-order) ............................................................. 14

Fig. 2.2.5 Structure of Timer X mode register ............................................................................ 15

Fig. 2.2.6 Structure of Timer Y (low-order, high-order) ............................................................. 16

Fig. 2.2.7 Structure of Timer Y mode register ............................................................................ 17

Fig. 2.2.8 Structure of Interrupt request register B .................................................................... 18

Fig. 2.2.9 Structure of Interrupt request register C ................................................................... 18

Fig. 2.2.10 Structure of Interrupt control register B ................................................................... 19

Fig. 2.2.11 Structure of Interrupt control register C ................................................................... 19

Fig. 2.2.12 Timers connection and setting of division ratios .................................................... 21

Fig. 2.2.13 Related registers setting ............................................................................................ 22

Fig. 2.2.14 Control procedure ........................................................................................................ 23

Fig. 2.2.15 Peripheral circuit example .......................................................................................... 24

Fig. 2.2.16 Timers connection and setting of division ratios .................................................... 24

Fig. 2.2.17 Relevant registers setting .......................................................................................... 25

Fig. 2.2.18 Control procedure ........................................................................................................ 26

Fig. 2.2.19 How to measure frequency ........................................................................................ 27

Fig. 2.2.20 Related registers setting ............................................................................................ 28

Fig. 2.2.21 Control procedure ........................................................................................................ 29

Fig. 2.2.22 Timers connection and setting of division ratios .................................................... 30

Fig. 2.2.23 Relevant registers setting .......................................................................................... 31

Fig. 2.2.24 Control procedure (1) ................................................................................................. 32

Fig. 2.2.25 Control procedure (2) ................................................................................................. 33

Fig. 2.2.26 Circuit example ............................................................................................................ 34

Fig. 2.2.27 Related registers setting ............................................................................................ 35

Fig. 2.2.28 Control procedure ........................................................................................................ 36

List of figures

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