7641 datasheet(32/385 Pages) RENESAS

32 / 385 page

Rev.2.00

Aug 28, 2006

page 15 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION

I/O PORTS

Direction Registers

The I/O ports P0–P8 have direction registers which determine the

input/output direction of each individual pin. Each bit in a direction

or output port.

When “0” is written to the bit corresponding to a pin, that pin be-

comes an input pin. When “1” is written to that bit, that pin becomes

an output pin.

If data is read from a pin set to output, the value of the port output

latch is read, not the value of the pin itself. Pins set to input are float-

ing. If a pin set to input is written to, only the port output latch is

written to and the pin remains floating.

Slew Rate Control

By setting bits 0 to 5 of the port control register (address 001016) to

“1”, slew rate control is enabled. VIHL or CMOS level can be used as

a port P2 input level; CMOS or TTL level can be used as an input

level of master CPU bus interface.

Pull-up Control

By setting the port P2 pull-up control register (address 001216), pull-

up of each pin of port P2 can be controlled with a program.

However, the contents of port P2 pull-up control register do not affect

ports programmed as the output ports but as the input ports.

Fig. 11 Structure of port control and port P2 pull-up control

registers

Port control register (address 001016)

PTC

Port P0 to P3 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P4 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P5 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P6 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P7 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P8 slew rate control bit (Note 1)

0: Disabled

1: Enabled

Port P2 input level select bit

0: Reduced VIHL level input (Note 2)

1: CMOS level input

Master CPU bus input level select bit

0: CMOS level input

1: TTLlevel input

Notes 1: The slew rate function can reduce di/dt by modifying an internal

buffer structure.

2: The characteristics of VIHL level is basically the same as that of

TTL level. But, its switching center point is a little higher than

TTL’s. Refer to section “Recommended operating conditions”.

Port P2 pull-up control register

(address 001216) PUP2

Port P20 pull-up control bit

0: Disabled

1: Enabled

Port P21 pull-up control bit

0: Disabled

1: Enabled

Port P22 pull-up control bit

0: Disabled

1: Enabled

Port P23 pull-up control bit

0: Disabled

1: Enabled

Port P24 pull-up control bit

0: Disabled

1: Enabled

Port P25 pull-up control bit

0: Disabled

1: Enabled

Port P26 pull-up control bit

0: Disabled

1: Enabled

Port P27 pull-up control bit

0: Disabled

1: Enabled

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