7641 datasheet(46/385 Pages) RENESAS

46 / 385 page

Rev.2.00

Aug 28, 2006

page 29 of 113

7641 Group

REJ09B0336-0200

HARDWARE

FUNCTIONAL DESCRIPTION

SERIAL INTERFACE

Serial I/O

The serial I/O can be used only for clock synchronous serial I/O.

The transmitter and the receiver must use the same clock. If the

internal clock is used, transfer is started by a write signal to the

serial I/O shift register.

[Serial I/O Control Register 1 (SIOCON1)] 002B16

[Serial I/O Control Register 2 (SIOCON2)] 002C16

Each of the serial I/O control registers 1 and 2 contains eight bits

which control various serial I/O functions.

Fig. 23 Structure of serial I/O control registers 1, 2

Serial I/O control register 1 (address 002B16)

SIOCON1

Internal synchronous clock select bits (Note 1)

b2b1b0

0 0 0: Internal clock divided by 2

0 0 1: Internal clock divided by 4

0 1 0: Internal clock divided by 8

0 1 1: Internal clock divided by 16

1 0 0: Internal clock divided by 32

1 0 1: Internal clock divided by 64

1 1 0: Internal clock divided by 128

1 1 1: Internal clock divided by 256

Serial I/O port select bit

0: I/O port

1: STXD, SCLK signal output

SRDY output select bit

0: I/O port

1: SRDY signal output

Transfer direction select bit

0: LSB first

1: MSB first

Synchronous clock select bit

0: External clock

1: Internal clock

STXD output channel control bit

0: CMOS output

1: N-channel open drain output

Notes 1: The source of serial I/O internal synchronous clock can be selected by bit 1 of

serial I/O control register 2.

2 : To set the slave mode, also set bit 4 of serial I/O control register 1 to “1”.

Serial I/O control register 2 (address 002C16)

SIOCON2

SPI mode select bit

0: Normal serial I/O mode

1: SPI compatible mode (

Note 2)

Serial I/O internal clock select bit

1: SCSGCLK

SRXD input enable bit

0: SRXD input disabed

1: SRXD input enabed

Clock polarity select bit (CPoL)

0: SCLK starting at “L”

1: SCLK starting at “H”

Clock phase select bit (CPha)

0: Serial transfer starting at falling edge of SRDY

1: Serial transfer starting afer a half cycle of SCLK

passed at falling edge of SRDY

Reserved bits (“0” at read/write)

000

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