| поискавой системы для электроныых деталей |
|
HD6432351 датащи(PDF) 197 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD6432351 датащи(HTML) 197 Page - Renesas Technology Corp |
|
197 / 1025 page ![]() Section 6 Bus Controller Rev. 3.00 Sep 15, 2006 page 163 of 988 REJ09B0330-0300 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.7 DRAM Interface Pins Pin With DRAM Setting Name I/O Function HWR WE Write enable Output When 2-CAS system is set, write enable for DRAM space access. LCAS LCAS Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access CS2 RAS2 Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space. CS3 RAS3 Row address strobe 3 Output Row address strobe when area 3 is designated as DRAM space. CS4 RAS4 Row address strobe 4 Output Row address strobe when area 4 is designated as DRAM space. CS5 RAS5 Row address strobe 5 Output Row address strobe when area 5 is designated as DRAM space. CAS UCAS Upper column address strobe Output Upper column address strobe for DRAM space access WAIT WAIT Wait Input Wait request signal A12 to A0 A12 to A0 Address pins Output Row address/column address multiplexed output D15 to D0 D15 to D0 Data pins I/O Data input/output pins |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |