HD6432351 datasheet(196/1025 Pages) RENESAS

196 / 1025 page

Section 6 Bus Controller

Rev. 3.00 Sep 15, 2006 page 162 of 988

REJ09B0330-0300

6.5.3

Address Multiplexing

With DRAM space, the row address and column address are multiplexed. In address multiplexing,

the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6

shows the relation between the settings of MXC1 and MXC0 and the shift size.

Table 6.6

Address Multiplexing Settings by Bits MXC1 and MXC0

MCR

Address Pins

MXC1 MXC0 Shift Size A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

8 bits

A23 to A13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8

Row

address

9 bits

A23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9

10 bits

A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10

Setting

prohibited

—

— —

—

— —

—

— —

—

— —

—

Column

address

—

A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

6.5.4

Data Bus

If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is

designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM

space. In 16-bit DRAM space,

×16-bit configuration DRAM can be connected directly.

In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM

space both the upper and lower halves of the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data

Size and Data Alignment.

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