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HD6432351 датащи(PDF) 125 Page - Renesas Technology Corp |
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HD6432351 датащи(HTML) 125 Page - Renesas Technology Corp |
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125 / 1025 page ![]() Section 5 Interrupt Controller Rev. 3.00 Sep 15, 2006 page 91 of 988 REJ09B0330-0300 Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2350 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: • Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). • Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. • Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. • Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. • DTC and DMAC control DTC and DMAC activation is performed by means of interrupts. |
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