HD6432351 datasheet(109/1025 Pages) RENESAS

109 / 1025 page

Section 3 MCU Operating Modes

Rev. 3.00 Sep 15, 2006 page 75 of 988

REJ09B0330-0300

3.3.4

Mode 4

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port

F carries bus control signals.

The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if

8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.

3.3.5

Mode 5

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.

Ports A, B and C function as an address bus, port D function as a data bus, and part of port F

carries bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at

least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16

bits and port E becomes a data bus.

3.3.6

Mode 6 (H8S/2351 Only)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.

Ports A, B and C function as input ports immediately after a reset. They can each be set to output

addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D

functions as a data bus, and part of port F carries bus control signals.

The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at

least one area is designated for 16 bit access by the bus controller, the bus mode switches to 16

bits and port E becomes a data bus.

3.3.7

Mode 7 (H8S/2351 Only)

The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,

but external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

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