HD6432351 datasheet(108/1025 Pages) RENESAS

108 / 1025 page

Section 3 MCU Operating Modes

Rev. 3.00 Sep 15, 2006 page 74 of 988

REJ09B0330-0300

3.3

Operating Mode Descriptions

3.3.1

Mode 1

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and

8-bit bus mode is set, immediately after a reset.

Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries

bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus

mode switches to 16 bits and port E becomes a data bus.

3.3.2

Mode 2 (H8S/2351 Only)

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and

8-bit bus mode is set. immediately after a reset.

Ports B and C function as input ports immediately after a reset. They can each be set to output

addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D

functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit

access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a

data bus.

The amount of on-chip ROM that can be used is limited to 56 kbytes.

3.3.3

Mode 3 (H8S/2351 Only)

The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but

external addresses cannot be accessed.

All I/O ports are available for use as input-output ports.

The amount of on-chip ROM that can be used is limited to 56 kbytes.

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