M16CSLASH29 datasheet(290/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 266

Setting value of CCR4 to CCR0

SCL frequency (at VIIC=4MHz, unit : kHz) (1)

CCR4 CCR3 CCR2 CCR1 CCR0

Standard clock mode

High-speed clock mode

Setting disabled

- (2)

333

- (2)

250

100

400 (3)

83.3

166

500 / CCR value (3)

1000 / CCR value (3)

17.2

34.5

16.6

33.3

16.1

32.3

NOTES:

The duty of the SCL clock output is 50 %. The duty becomes 35 to 45 % only when high-speed

clock mode is selected and the CCR value = 5 (400 kHz, at VIIC = 4 MHz). “H” duration of the

clock fluctuates from –4 to +2 I2C system clock cycles in standard clock mode, and fluctuates from

–2 to +2 I2C system clock cycles in high-speed clock mode. In the case of negative fluctuation,

the frequency does not increase because the “L” is extended instead of “H” reduction. These are

the values when the SCL clock synchronization by the synchronous function is not performed.

The CCR value is the decimal notation value of the CCR4 to CCR0 bits.

Each value of the SCL frequency exceeds the limit at VIIC = 4 MHz or more. When using these

setting values, use VIIC = 4 MHz or less. Refer to Figure 16.6.

The data formula of SCL frequency is described below:

VIIC/(8 x CCR value) Standard clock mode

VIIC/(4 x CCR value) High-speed clock mode (CCR value

≠ 5)

VIIC/(2 x CCR value) High-speed clock mode (CCR value = 5)

Do not set 0 to 2 as the CCR value regardless of the VIIC frequency. Set 100 kHz (max.) in

standard clock mode and 400 kHz (max.) in high-speed clock mode to the SCL frequency by

setting the CCR4 to CCR0 bits.

Table 16.3 Setting values of S20 register and SCL frequency

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